scholarly journals Design and implementation of CNTFET based ternary 1x1 memories

2019 ◽  
Vol 8 (3) ◽  
pp. 175 ◽  
Author(s):  
S.Tamil Selvan ◽  
M. Sundararajan
Keyword(s):  
High Performance ◽  
Data Access ◽  
Cmos Technology ◽  
Access Time ◽  
The Novel ◽  
Design And Implementation ◽  
Technology Process ◽  
Sram Cell ◽  
And Performance ◽  
Power Application

In this paper presented Design and implementation of CNTFET based Ternary 1x1 RAM memories high-performance digital circuits. CNTFET Ternary 1x1 SRAM memories is implement using 32nm technology process. The CNTFET decresase the diameter and performance matrics like delay,power and power delay, The CNTFET Ternary 6T SRAM cell consists of two cross coupled Ternary inverters one is READ and another WRITE operations of the Ternary 6T SRAM cell are performed with the Tritline using HSPICE and Tanner tools in this tool is performed high accuracy. The novel based work can be used for Low Power Application and Access time is less of compared to the conventional CMOS Technology. The CNTFET Ternary 6T SRAM array module (1X1) in 32nm technology consumes only 0.412mW power and data access time is about 5.23ns.

The Ballistic Air Cleaner Concept for Army Vehicular Gas Turbines

1968 ◽  
Author(s):  
L. J. DuRocher ◽  
Hugo Giannotti
Keyword(s):  
Boundary Layer ◽  
Gas Turbines ◽  
High Performance ◽  
The Novel ◽  
Air Cleaner ◽  
And Performance

The air cleaner requirements for Army vehicular gas turbines are developed and performance of the novel boundary-layer ballistic type separator is discussed. A unit specifically designed for gas turbines demonstrates high performance. This separator is compared and field results are included.

scholarly journals JAliEn: the new ALICE high-performance and high-scalability Grid framework

2019 ◽  
Vol 214 ◽  
pp. 03037
Author(s):  
M. Martinez Pedreira ◽  
C. Grigoras ◽  
V. Yurchenko
Keyword(s):  
Data Processing ◽  
High Performance ◽  
Data Access ◽  
Performance Measurements ◽  
Alice Experiment ◽  
Grid Middleware ◽  
Software Upgrades ◽  
Order Of Magnitude ◽  
And Performance ◽  
And Storage

The ALICE experiment will undergo extensive hardware and software upgrades for the LHC Run3. This translates in significant increase of the CPU and storage resources required for data processing, and at the same time the data access rates will grow linearly with the amount of resources. JAliEn (Java ALICE Environment) is the new Grid middleware designed to scale-out horizontally to fulfil the computing needs of the upgrade, and at the same time to modernize all parts of the distributed system software. This paper will present the architecture of the JAliEn framework, the technologies used and performance measurements. This work will also describe the next generation solution that will replace our main database backend, the AliEn File Catalogue. The catalogue is an integral part of the system, containing the metadata of all files written to the distributed Grid storage and also provides powerful search and data manipulation tools. As for JAliEn, the focus has been put onto horizontal scalability, with the aim to handle near exascale data volumes and order of magnitude more workload than the currently used Grid middleware. Lastly, this contribution will present how JAliEn manages the increased complexity of the tasks associated with the new ALICE data processing and analysis framework (ALFA) and multi-core environments.

A novel 0.79 μm/sup 2/ SRAM cell by KrF lithography and high performance 90 nm CMOS technology for ultra high speed SRAM

2003 ◽  
Author(s):  
Soon-Moon Jung ◽  
Hyungshin Kwon ◽  
Jaehun Jeong ◽  
Wonseok Cho ◽  
Sungbong Kim ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Cmos Technology ◽  
Ultra High Speed ◽  
Sram Cell

scholarly journals Energy Efficient SRAM

2019 ◽  
Vol 8 (9) ◽  
pp. 1086-1091
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Static Noise Margin ◽  
Noise Margin ◽  
And Performance ◽  
The Stability ◽  
Static Noise

Memories are an essential unit of any digital circuit, thus their power consumption must be considered during the designing process of the cells. To improve performance, reduce delay and increase stability, it is advisable to decrease the power consumed by the memory. Due to high demand of speed, high performance, there’s a need to decrease the size of the device, thereby increasing the devices placed per chip. This high integration makes chips more complex but improves device performance. Design of SRAM cells with speed and low power is crucial so as to replace DRAMs. The layout of SRAM has advanced to meet the requirements of the present industry in accordance with parameters like delay, power consumption and stability etc. This paper presents the aim of analyzing different technologies used to make SRAM more efficient in terms of parameters such as static noise margin, latency and dissipation of power. The stability investigation of SRAM cells are usually derived from the Static Noise Margin (SNM) analysis. Here we observe a SRAM design which has used dynamic logic and pass transistor logic. We further study the effects made on this design by employing various technologies such as AVL-S, AVL-G, AVL and MT-CMOS, at 180nm CMOS technology to achieve enhancements in delay, power consumption and performance. The proposed circuits are simulated and the results obtained have been analyzed to show significant improvement over conventional SRAM designs. Cadence Virtuoso simulation is used to confirm all the results obtained in this paper for the simulation of 180 nm CMOS technology SRAMs.

scholarly journals An Innovative Design of an Integrated MED-TVC and Reverse Osmosis System for Seawater Desalination: Process Explanation and Performance Evaluation

Processes ◽  
2020 ◽  
Vol 8 (5) ◽  
pp. 607
Author(s):  
Omer Mohamed Abubaker Al-hotmani ◽  
Mudhar Abdul Alwahab Al-Obaidi ◽  
Yakubu Mandafiya John ◽  
Raj Patel ◽  
Iqbal Mohammed Mujtaba
Keyword(s):  
Reverse Osmosis ◽  
High Performance ◽  
Integrated System ◽  
Operating Conditions ◽  
The Novel ◽  
Innovative Design ◽  
High Performance Systems ◽  
Total Productivity ◽  
And Performance ◽  
Vapour Compression

In recent times two or more desalination processes have been combined to form integrated systems that have been widely used to resolve the limitations of individual processes as well as producing high performance systems. In this regard, a simple integrated system of the Multi Effect Distillation (MED)/Thermal Vapour Compression (TVC) and Permeate Reprocessing Reverse Osmosis (PRRO) process was developed by the same authors and confirmed its validity after a comparison study against other developed configurations. However, this design has a considerable amount of retentate flowrate and low productivity. To resolve this issue, two novel designs of MED and double reverse osmosis (RO) processes including Permeate and Retentate Reprocessing designs (PRRP and RRRO) are developed and modelled in this paper. To systematically assess the consistency of the presented designs, the performance indicators of the novel designs are compared against previous simple designs of MED and PRRO processes at a specified set of operating conditions. Results show the superiority of the integrated MED and double permeate reprocessing design. This has specifically achieved both economic and environmental advantages where total productivity is increased by around 9% and total retentate flowrate (disposed to water bodies) is reduced by 5% with a marginally reduced energy consumption.

DESIGN AND ANALYSIS OF A NOVEL LOW PDP FULL ADDER CELL

2011 ◽  
Vol 20 (03) ◽  
pp. 439-445 ◽  
Author(s):  
M. H. GHADIRY ◽  
ABU KHARI A'AIN ◽  
M. NADI S.
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Accurate Analysis ◽  
And Performance ◽  
Full Swing ◽  
Driving Capability

This paper, presents a new full-swing low power high performance full adder circuit in CMOS technology. It benefits from a full swing XOR-XNOR module with no feedback transistors, which decreases delay and power consumption. In addition, high driving capability of COUT module and low PDP design of SUM module contribute to more PDP reduction in cascaded mode. In order to have accurate analysis, the new circuit along with several well-known full adders from literature have been modeled and compared with CADENCE. Comparison consists of power consumption, performance, PDP, and area. Results show that there are improvements in both power consumption and performance. This design trades area with low PDP.

A Fuel Cell Stack Architecture to Make all Cells Have Equal Operational Conditions and Performance

2012 ◽  
Author(s):  
Hong Liu ◽  
Peiwen Li ◽  
Alexandra Hartz
Keyword(s):  
Fuel Cell ◽  
High Performance ◽  
Proton Exchange Membrane ◽  
Experimental Tests ◽  
Proton Exchange ◽  
The Novel ◽  
Fuel Cell Stack ◽  
Operational Conditions ◽  
And Performance ◽  
Exchange Membrane

This paper presents a novel architecture for a proton-exchange membrane (PEM) fuel cell stack, which is based on the concept that every cell in the stack works at the same condition and thus each cell has the same contribution to the overall output voltage and power. To meet this proposed requirement, special flow distributors were used to evenly distribute fuel and airflow to every fuel cell in the stack. Details of the flow distributor and experimental tests of a four-cell fuel cell stack are presented in the paper. The experimental results demonstrated the desired high performance of the fuel cell stack. It is proved that the novel architecture for fuel cell stack is successful and of significance to the development of high performance fuel cell stacks.

scholarly journals Design and Implementation of High Performance and Low Power Mixed Logic Line Decoders

2019 ◽  
Vol 8 (6S4) ◽  
pp. 635-640
Keyword(s):  
High Performance ◽  
Data Transfer ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Analog To Digital ◽  
Delay Performance ◽  
And Performance ◽  
Almost All

The decoders are widely used in the logical circuits, data transfer circuits and analog to digital conversions. A mixed logic design methods for the line decoders are used to combining the transmission gate logic, pass transistor logic, and complementary metal-oxide semiconductor (CMOS) technology provides desired operation and performance. A novel topology is presented for the 2 to 4 decoder requires a fourteen transistor topology aiming on reducing the transistor count and operating power and a fifteen transistor topology aiming on high power and low delay performance. The standard and inverting decoders are designed in each of the case, gives a total of four new designs circuits. All the proposed decoders have compact transistor count compared to their conservative CMOS technologies. Finally, a variety of proposed designs present a noteworthy improvement in operating power and propagation delay, outperforming CMOS in almost all the cases.

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