Ultra-thin (EOT=3Å) and low leakage dielectrics of La-alminate directly on si substrate fabricated by high temperature deposition

ABSTRACTTa2O5 films of high reliability and low leakage current density were obtained by low temperature deposition and subsequent high temperature oxygen anneal. At higher temperatures than 410°C, growth was governed by the formation of radicals in gas phase and oxidation on the surface, while at lower temperatures by the dissociation of reactant on the surface of substrates. As a result, the films deposited at lower temperatures had undensified structures, and contained more carbon that might be a leakage current source in Ta2O5 film. During post-deposition heat treatment in 800°C oxidating ambient, carbon was removed away and silicon was diffused from the substrate into the Ta2O5 film efficiently for its as-grown porous structure. After oxygen anneal, low temperature films get denser and are crystallized to mixed phase of orthorhombic and hexagonal Ta2O5, while high temperature films crystallized to orthorhombic single phase. Ta2O5 capacitor with low temperature films showed superior leakage characteristics applicable to sub-half micron memory devices.

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The reaction of amorphous Ni-Nb films with Si in the presence of a native SiO2 layer

Proceedings, annual meeting, Electron Microscopy Society of America ◽

10.1017/s0424820100176459 ◽

1990 ◽

Vol 48 (4) ◽

pp. 664-665

Author(s):

N. Rozhanski ◽

A. Barg

Keyword(s):

High Temperature ◽

Crystallization Temperature ◽

Diffusion Barriers ◽

Sio2 Layer ◽

Si Substrate ◽

Cross Sectional ◽

Plan View ◽

Temperature Range ◽

Sputter Deposited

Amorphous Ni-Nb alloys are of potential interest as diffusion barriers for high temperature metallization for VLSI. In the present work amorphous Ni-Nb films were sputter deposited on Si(100) and their interaction with a substrate was studied in the temperature range (200-700)°C. The crystallization of films was observed on the plan-view specimens heated in-situ in Philips-400ST microscope. Cross-sectional objects were prepared to study the structure of interfaces.The crystallization temperature of Ni5 0 Ni5 0 and Ni8 0 Nb2 0 films was found to be equal to 675°C and 525°C correspondingly. The crystallization of Ni5 0 Ni5 0 films is followed by the formation of Ni6Nb7 and Ni3Nb nucleus. Ni8 0Nb2 0 films crystallise with the formation of Ni and Ni3Nb crystals. No interaction of both films with Si substrate was observed on plan-view specimens up to 700°C, that is due to the barrier action of the native SiO2 layer.

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Reliability Implications of Defects in High Temperature Annealed Si/SiO2/Si Structures

MRS Proceedings ◽

10.1557/proc-338-3 ◽

1994 ◽

Vol 338 ◽

Cited By ~ 1

Author(s):

W. L. Warren ◽

D. M. Fleetwood ◽

M. R. Shaneyfelt ◽

P. S. Winokur ◽

R. A. B. Devine ◽

...

Keyword(s):

High Temperature ◽

Chemical Potential ◽

Field Effect Transistors ◽

Radiation Sensitivity ◽

Oxide Semiconductor ◽

Interfacial Region ◽

Si Substrate ◽

Paramagnetic Defect ◽

Chemical Potential Difference ◽

Hole Trapping

ABSTRACTHigh-temperature post-oxidation annealing of poly-Si/SiO2/Si structures such as metal-oxidesemiconductor capacitors and metal-oxide-semiconductor field effect transistors is known to result in enhanced radiation sensitivity, increased 1/f noise, and low field breakdown. We have studied the origins of these effects from a spectroscopic standpoint using electron paramagnetic resonance (EPR) and atomic force microscopy. One result of high temperature annealing is the generation of three types of paramagnetic defect centers, two of which are associated with the oxide close to the Si/SiO2 interface (oxygen-vacancy centers) and the third with the bulk Si substrate (oxygen-related donors). In all three cases the origin of the defects may be attributed to out-diffusion of O from the SiO2 network into the Si substrate with associated reduction of the oxide. We present a straightforward model for the interfacial region which assumes the driving force for O out-diffusion is the chemical potential difference of the O in the two phases (SiO2 and the Si substrate). Experimental evidence is provided to show that enhanced hole trapping and interface-trap and border-trap generation in irradiated high-temperature annealed Si/SiO2/Si systems are all related either directly, or indirectly, to the presence of oxygen vacancies.

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A Novel Low Temperature Self-Aligned Ti Silicide Technology for Sub-0.18 μm Cmos Devices

MRS Proceedings ◽

10.1557/proc-525-313 ◽

1998 ◽

Vol 525 ◽

Cited By ~ 1

Author(s):

L. P. Ren ◽

P. Liu ◽

G. Z. Pan ◽

Jason C. S. Woo

Keyword(s):

High Temperature ◽

Low Temperature ◽

Amorphous Layer ◽

Sharp Interface ◽

Silicide Formation ◽

Si Substrate ◽

Metal Thickness ◽

Substrate Doping

ABSTRACTA novel low temperature self-aligned Ti silicidation with Ge+ pre-amorphization implant (PAI) is presented. Compared to conventional high temperature PAM silicidation, the advantages of Ti salicidation at temperatures below the recrystallization of a pre-amorphized layer are: (1) C49 TiSi2 silicide formation occurs only in the pre-amorphized layer so that the silicide depth can be well controlled, forming a very sharp interface between the silicide and the Si substrate; (2) Ti just reacts with the amorphous layer, avoiding the so-called bridging issue in which the silicide grows laterally over the isolation or spacer; (3) the effects of metal thickness and substrate doping on silicide formation are suppressed.

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Comparison of charge trapping in undoped oxides made by low- and high-temperature deposition techniques

IEEE Transactions on Nuclear Science ◽

10.1109/23.983180 ◽

2001 ◽

Vol 48 (6) ◽

pp. 2107-2113 ◽

Cited By ~ 4

Author(s):

B.J. Mrstik ◽

H.L. Hughes ◽

R.K. Lawrence ◽

P.J. McMarr ◽

P. Gouker

Keyword(s):

High Temperature ◽

Charge Trapping ◽

Temperature Deposition ◽

Deposition Techniques

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GaN-Based HEMTs on Large-Diameter Si Substrate for Next Generation of High Power/High Temperature Devices

Nano-Semiconductors ◽

10.1201/9781315217468-23 ◽

2018 ◽

pp. 475-498

Keyword(s):

High Temperature ◽

High Power ◽

Large Diameter ◽

Next Generation ◽

Si Substrate

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A High Temperature 4H-SiC Voltage Reference for Depletion Mode GaN-Based Circuits

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2380-4491.2017.hiten.118 ◽

2017 ◽

Vol 2017 (HiTEN) ◽

pp. 000118-000121

Author(s):

ZiHao Zhang ◽

Jebreel M. Salem ◽

Dong Sam Ha

Keyword(s):

High Temperature ◽

High Temperatures ◽

Oil And Gas ◽

Supply Voltage ◽

Reference Voltage ◽

Voltage Reference ◽

Voltage Range ◽

Oil And Gas Exploration ◽

Low Leakage ◽

Temperature Applications

Abstract High temperature electronics are highly demanded for many applications such as automotive, space, and oil and gas exploration. Electronic circuits for those applications are required to operate reliably without using bulky cooling systems. Circuits based on silicon (Si) suffer from high leakage currents at high temperatures. Silicon Carbide (SiC) circuits, on the other hand, are suitable for high temperature applications due to the wide bandgap and offer high breakdown voltage and low leakage current. This paper presents a negative voltage reference for high temperature applications using commercial-off-the-shelf (COTS) 4H-SiC transistors. The proposed voltage reference adopts Widlar bandgap reference topology, and it aims to provide a negative reference voltage for Gallium Nitride (GaN) circuits operating at high temperatures. Measurement results indicate that the proposed circuit provides a negative reference voltage with a low temperature coefficient of 42 ppm/°C for temperatures ranging from 25 °C to 250 °C. The proposed circuit also operates reliably for a wide supply voltage range of −7.5 V to −15 V for the temperature range.

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High-Temperature Trench Capacitors, Using Thin-Film ALD Dielectrics

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/hiten-session4-paper4_2 ◽

2015 ◽

Vol 2015 (HiTEN) ◽

pp. 000130-000133 ◽

Cited By ~ 1

Author(s):

Dorothee Dietz ◽

Yusuf Celik ◽

Andreas Goehlich ◽

Holger Vogt ◽

Holger Kappert

Keyword(s):

High Temperature ◽

Leakage Current ◽

Automobile Industry ◽

Elevated Temperatures ◽

Atomic Layer ◽

Operating Voltage ◽

Low Leakage ◽

Low Leakage Current ◽

Layer Deposition ◽

Soft Breakdown

High-temperature passive electronic becomes more and more important, e.g. in the field of deep drilling, aerospace or in automobile industry. For these applications, capacitors are needed, which are able to withstand temperatures up to 300 °C, which exhibit a low leakage current at elevated temperatures, a breakdown voltage above the intended operating voltage and a high capacitive density value. In this paper, investigations of 3D-integration and atomic layer deposition (ALD) techniques to achieve these features are presented. A highly n-doped Si-substrate acts as a bottom electrode. Medium- and high-k dielectrics represent the insulator and the upper electrode consists of Ru, TiN or TiAlCN. The materials can be used at elevated temperatures. At room temperature, the leakage current is less than 10 pA/mm2 without showing a soft-breakdown up to ± 15 V, indicating the absence of Fowler-Nordheim tunneling. At 300 °C and at 3 V the leakage current amounts about 1 nA/mm2 and at 5 V a soft-breakdown is detected.

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