Design of a Robust ESD Protection Device using 6H-SiC Nano-Scale GGNMOS

With the continuous shrinking of the technological nodes and the introduction of new device concepts and materials, integrated circuits (IC) are becoming more vulnerable to electrostatic discharge (ESD) induced failures which is one of the major concerns in designing robust ICs. Therefore, to improve the reliability of the ICs against ESD induced failures, extensive research efforts are being conducted. In this paper, we have presented a 6H-SiC based nano-scale grounded-gate NMOS (ggNMOS) ESD protection device and compared the results with the 3C-SiC-based ggNMOS. To design a robust ESD protection device, some critical device parameters, such as substrate doping concentration, source/drain doping concentration, drain to substrate contact spacing, and substrate contact resistance should be optimized. The ESD protection characteristics can be improved by utilizing the near punch-through effect. It was found that the trigger voltage and hold voltage are higher in 6H-SiC than the 3C-SiC having identical device parameters. 6H-SiC shows better voltage clamping performance as the turn-on resistance of 6H-SiC is smaller compared to the 3C-SiC material. Therefore, the results show that 6H-SiC has a better performance compared to 3C-SiC and due to its higher bandgap, and can be used as a good ESD protection device. All the simulations are carried out using the Silvaco ATLAS device simulator.

Спектральные и электрические свойства светодиодных гетероструктур с активной областью на основе InAs

The results of the study of optical and structural properties of epitaxial InAs layers grown on an n-InAs substrate, and spectral and electrical properties of light-emitting diode (LED) heterostructures with an InAs active layer and various design and chemical composition of barrier layers are presented; the properties of heterostructures were studied in the temperature range 4.2−300 K. A significant influence of the degree of substrate doping and the properties of heterointerfaces on the form of emission spectra and power characteristics of heterostructures is shown. The mechanisms of the carrier transport are studied, and the prevalence of the diffusion component of the current at temperatures above 200 K and the presence of the tunneling component at lower temperatures are shown.

Influence of Substrate Type and Dose of Implanted Ions on the Electrical Parameters of Silicon in Terms of Improving the Efficiency of Photovoltaic Cells

The main goal of this work was to conduct a comparative analysis of the electrical properties of the silicon implanted with neon ions, depending on the dose of ions and the type of substrate doping, for the possibility of generating additional energy levels by ion implantation in terms of improving the efficiency of photovoltaic cells made on its basis. The article presents the results of research on the capacitance and conductance of silicon samples doped with boron and phosphorus, the structure of which was modified in the implantation process with Ne+ ions with energy E = 100 keV and different doses. The analysis of changes in electrical properties recorded at the annealing temperature of the samples Ta = 298 K, 473 K, 598 K, 673 K, and 873 K, concerned the influence of the test temperature in the range from 203 K to 373 K, as well as the frequency f from 100 Hz to 10 MHz, and voltage U from 0.25 V to 2 V. It was possible to detect intermediate bands in the tested samples and determine their position in the band gap by estimating the activation energy value. By means of implantation, it is possible to modify the width of the silicon energy gap, the value of which directly affects the efficiency of the photovoltaic cell made on its basis. By introducing appropriate defects into the silicon crystal lattice, contributing to a change in the value of the energy gap Eg, it is possible to increase the efficiency of the solar cell. On the basis of the obtained results, it can be seen that the highest activation energies are achieved for samples doped with phosphorus.

Reducing On-Resistance for SiC Diodes by Thin Wafer and Laser Anneal Technology

This work presents the influence of Thin Wafer und Laser Anneal Technology on the electrical performance of 4HSiC devices. Substrate thinning and backside ohmic contact formation via laser annealing were successfully applied to in-house designed and manufactured 6 A 650 V SiC diodes at IISB, improving its forward characteristics. The given devices exhibit an on-state voltage drop (VF) reduction from 1.78 V to 1.62 V at 6 A rated current while maintaining blocking capabilities of more than 1.1 kV with leakage currents less than 1 μA at 650 V nominal voltage. On-resistance (RON) was lowered by approx. 30 % to 90 mΩ and 60 % to 12 mΩ in Schottky and conductivity modulation state, respectively. Wafer thinning also allows reducing the influence of non-homogeneous distributed substrate doping concentrations, leading to a more narrow distribution of the forward characteristics of the devices across the wafer.

Bulk Junctionless Transistor (JLT) with Non-Uniform Doping: A high Performance and Scalable device

In this paper we have presented the non-uniformly doped bulk Junctionless transistor (JLT) and investigated bulk-JLT and SOI-JLT with non-uniform doping in terms of its electrical performance parameters and short channel effects (SCEs) parameters comparatively. Effective thickness of channel depends on non-uniform doping distribution parameters and this affects the performance of bulk-JLT notably, however it is not so in case of SOI-JLT. The effect of non-uniform doping on electrical characteristics of JLTs (bulk and SOI) in terms of Subthreshold Slope (SS), ON-current, OFF-Current and ON/OFF current ratio has been investigated, and the non-uniformly doped bulk-JLT exhibits high ON/OFF ratio (109 for 20 nm Gate Length). Moreover, the non-uniformly doped bulk-JLT also shows improved short-channel effects (SCEs) parameters (such as Drain Induced Barrier Lowering, Threshold Voltage variations etc.) compared to SOI-JLT. Lastly, the effect of standard deviation, dielectric constant, substrate doping, and well biasing on the device performance are examined to further improve the performance of bulk-JLT independently.