Scalability of Fully Planar NAND Flash Memory Arrays Below 45nm

2009 ◽  
Author(s):  
Pieter Blomme ◽  
J. Van Houdt
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Memory Arrays

Random Telegraph Noise-Induced Sensitivity of Data Retention to Cell Position in the Programmed Distribution of NAND Flash Memory Arrays

2015 ◽  
Vol 36 (7) ◽  
pp. 678-680 ◽  
Author(s):  
Davide Resnati ◽  
Christian Monzio Compagnoni ◽  
Giovanni M. Paolucci ◽  
Carmine Miccoli ◽  
Alessandro S. Spinelli ◽  
...  
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Data Retention ◽  
Random Telegraph Noise ◽  
Cell Position ◽  
Telegraph Noise ◽  
Memory Arrays

Single Event Effects in NAND Flash Memory Arrays

2006 ◽  
Vol 53 (4) ◽  
pp. 1813-1818 ◽  
Author(s):  
G. Cellere ◽  
A. Paccagnella ◽  
A. Visconti ◽  
M. Bonanomi ◽  
S. Beltrami
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Single Event ◽  
Nand Flash Memory ◽  
Single Event Effects ◽  
Memory Arrays

scholarly journals Modeling of GIDL–Assisted Erase in 3–D NAND Flash Memory Arrays and Its Employment in NOR Flash–Based Spiking Neural Networks

2022 ◽  
pp. 43-53
Author(s):  
Gerardo Malavena
Keyword(s):  
Neural Networks ◽  
Flash Memory ◽  
Computational Effort ◽  
Spiking Neural Networks ◽  
Compact Model ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Memory Arrays ◽  
Tcad Simulations ◽  
Nor Flash

AbstractSince the very first introduction of three-dimensional (3–D) vertical-channel (VC) NAND Flash memory arrays, gate-induced drain leakage (GIDL) current has been suggested as a solution to increase the string channel potential to trigger the erase operation. Thanks to that erase scheme, the memory array can be built directly on the top of a $$n^+$$ n + plate, without requiring any p-doped region to contact the string channel and therefore allowing to simplify the manufacturing process and increase the array integration density. For those reasons, the understanding of the physical phenomena occurring in the string when GIDL is triggered is important for the proper design of the cell structure and of the voltage waveforms adopted during erase. Even though a detailed comprehension of the GIDL phenomenology can be achieved by means of technology computer-aided design (TCAD) simulations, they are usually time and resource consuming, especially when realistic string structures with many word-lines (WLs) are considered. In this chapter, an analysis of the GIDL-assisted erase in 3–D VC nand memory arrays is presented. First, the evolution of the string potential and GIDL current during erase is investigated by means of TCAD simulations; then, a compact model able to reproduce both the string dynamics and the threshold voltage transients with reduced computational effort is presented. The developed compact model is proven to be a valuable tool for the optimization of the array performance during erase assisted by GIDL. Then, the idea of taking advantage of GIDL for the erase operation is exported to the context of spiking neural networks (SNNs) based on NOR Flash memory arrays, which require operational schemes that allow single-cell selectivity during both cell program and cell erase. To overcome the block erase typical of nor Flash memory arrays based on Fowler-Nordheim tunneling, a new erase scheme that triggers GIDL in the NOR Flash cell and exploits hot-hole injection (HHI) at its drain side to accomplish the erase operation is presented. Using that scheme, spike-timing dependent plasticity (STDP) is implemented in a mainstream NOR Flash array and array learning is successfully demonstrated in a prototype SNN. The achieved results represent an important step for the development of large-scale neuromorphic systems based on mature and reliable memory technologies.

Investigation of the threshold voltage instability after distributed cycling in nanoscale NAND Flash memory arrays

2010 ◽  
Author(s):  
Christian Monzio Compagnoni ◽  
Carmine Miccoli ◽  
Riccardo Mottadelli ◽  
Silvia Beltrami ◽  
Michele Ghidotti ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Voltage Instability ◽  
Memory Arrays

Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

2012 ◽  
Vol E95.C (5) ◽  
pp. 837-841 ◽  
Author(s):  
Se Hwan PARK ◽  
Yoon KIM ◽  
Wandong KIM ◽  
Joo Yun SEO ◽  
Hyungjin KIM ◽  
...  
Keyword(s):  
Flash Memory ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Memory Array

Analysis on Hybrid SSD Configuration with Emerging Non-Volatile Memories Including Quadruple-Level Cell (QLC) NAND Flash Memory and Various Types of Storage Class Memories (SCMs)

2020 ◽  
Vol E103.C (4) ◽  
pp. 171-180
Author(s):  
Yoshiki TAKAI ◽  
Mamoru FUKUCHI ◽  
Chihiro MATSUI ◽  
Reika KINOSHITA ◽  
Ken TAKEUCHI
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory

scholarly journals Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han
Keyword(s):  
Neural Network ◽  
Error Correction ◽  
Error Detection ◽  
Flash Memory ◽  
Nand Flash ◽  
Data Reliability ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Noise Mitigation ◽  
Memory Channel

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

Sign in / Sign up

Export Citation Format

Share Document