Comparative analysis of DOIND approach with and without body biasing for leakage reduction in domino logic circuits

2015 ◽  
Author(s):  
Ambika Prasad Shah ◽  
Vaibhav Neema ◽  
Shreeniwas Daulatabad
Keyword(s):  
Comparative Analysis ◽  
Logic Circuits ◽  
Domino Logic ◽  
Leakage Reduction ◽  
Body Biasing

DOIND: a technique for leakage reduction in nanoscale domino logic circuits

2016 ◽  
Vol 37 (5) ◽  
pp. 055001 ◽  
Author(s):  
Ambika Prasad Shah ◽  
Vaibhav Neema ◽  
Shreeniwas Daulatabad
Keyword(s):  
Logic Circuits ◽  
Domino Logic ◽  
Leakage Reduction

Dual threshold voltage and sleep switch dual threshold voltage DOIND approach for leakage reduction in domino logic circuits

2017 ◽  
Vol 25 (5) ◽  
pp. 1639-1652 ◽  
Author(s):  
Ambika Prasad Shah ◽  
Vaibhav Neema ◽  
Shreeniwas Daulatabad ◽  
Praveen Singh
Keyword(s):  
Threshold Voltage ◽  
Logic Circuits ◽  
Domino Logic ◽  
Leakage Reduction ◽  
Dual Threshold Voltage

Performance evaluation of domino logic circuits for wide fan-in gates with FinFET

2018 ◽  
Vol 24 (8) ◽  
pp. 3341-3348 ◽  
Author(s):  
Ajay Kumar Dadoria ◽  
Kavita Khare ◽  
Uday Panwar ◽  
Anita Jain
Keyword(s):  
Performance Evaluation ◽  
Logic Circuits ◽  
Domino Logic

Analysis and characterization of leakage reduction methodologies for stacking, body biasing and DLS in 65 nm CMOS technology

2019 ◽  
Vol 102 (1) ◽  
pp. 1-8
Author(s):  
Dima Kilani ◽  
Baker Mohammad ◽  
Mohammad Alhawari ◽  
Hani Saleh ◽  
Mohammed Ismail
Keyword(s):  
Cmos Technology ◽  
Leakage Reduction ◽  
Body Biasing
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