Charge sharing fault detection for CMOS domino logic circuits

Author(s):  
C.H. Cheng ◽  
S.C. Chang ◽  
J.S. Wang ◽  
W.B. Jone
2017 ◽  
Vol 6 (2) ◽  
pp. 122-132
Author(s):  
Deepika Bansal ◽  
Brahmadeo Prasad Singh ◽  
Ajay Kumar

The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.


2020 ◽  
Vol 48 (8) ◽  
pp. 1346-1362
Author(s):  
Sapna Rani Ghimiray ◽  
Preetisudha Meher ◽  
Pranab Kishore Dutta
Keyword(s):  

2018 ◽  
Vol 24 (8) ◽  
pp. 3341-3348 ◽  
Author(s):  
Ajay Kumar Dadoria ◽  
Kavita Khare ◽  
Uday Panwar ◽  
Anita Jain

Author(s):  
M. Houshmand Kaffashian ◽  
R. Lotfi ◽  
K. Mafinezhad ◽  
H. Mahmoodi

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