Parasitic-aware design and optimization of CMOS RF integrated circuits

Author(s):  
R. Gupta ◽  
D.J. Allstot
10.1142/7260 ◽  
2010 ◽  
Author(s):  
Kiat Seng Yeo ◽  
Manh Anh Do ◽  
Chirn Chye Boon

2002 ◽  
Vol 49 (6) ◽  
pp. 1084-1086 ◽  
Author(s):  
J. Aguilera ◽  
J. Melendez ◽  
R. Berenguer ◽  
J.R. Sendra ◽  
A. Hernandez ◽  
...  

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 785
Author(s):  
Juan L. Castagnola ◽  
Fortunato C. Dualibe ◽  
Agustín M. Laprovitta ◽  
Hugo García-Vázquez

This work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in MOS 65 nm technology is taken as a case study in order to validate the approach. In addition, this methodology permits the identification of the best trade-off between the minimum noise figure and the maximum gain for the LNA in a very simple way.


2020 ◽  
Vol 56 (6) ◽  
pp. 280-282
Author(s):  
D. Mitra ◽  
S.B. Hamidi ◽  
P. Roy ◽  
C. Biswas ◽  
A. Biswas ◽  
...  

2009 ◽  
Vol 56 (9) ◽  
pp. 1882-1890 ◽  
Author(s):  
Munir M. El-Desouki ◽  
Samar M. Abdelsayed ◽  
M. Jamal Deen ◽  
Natalia K. Nikolova ◽  
Yaser M. Haddara

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