A Novel Test Application Scheme for High Transition Fault Coverage and Low Test Cost

2010 ◽  
Vol 29 (6) ◽  
pp. 966-976 ◽  
Author(s):  
Zhen Chen ◽  
Dong Xiang
Keyword(s):  
Fault Coverage ◽  
Test Cost ◽  
Test Application ◽  
Transition Fault ◽  
High Transition

scholarly journals On-chip Generation of Functional Tests with Reduced Delay and Power

2017 ◽  
Vol 6 (1) ◽  
pp. 36-46
Author(s):  
Hemanth Kumar Motamarri ◽  
B. Leela Kumari
Keyword(s):  
Test Generation ◽  
Fault Coverage ◽  
Pattern Generation ◽  
Functional Tests ◽  
Primary Input ◽  
Transition Fault ◽  
High Transition ◽  
On Chip

This paper describes different methods  on-chip test generation method for functional tests. The hardware was based on application of primary input sequences in order to allow the circuit to produce reachable states. Random primary input sequences were modeled to avoid repeated synchronization and thus yields varied sets of reachable states by implementing a decoder in between circuit and LFSR. The on-chip generation of functional tests require simple hardware and achieved high transition fault coverage for testable circuits. Further, power and delay can be reduced by using Bit Swapping LFSR (BS-LFSR). This technique yields less number of transitions for all pattern generation. Bit-swapping (BS) technique is less complex and more reliable to hardware miscommunications.

Concurrent Core Test Based on Partial Test Set Reusing

2014 ◽  
Vol 529 ◽  
pp. 359-363
Author(s):  
Xi Lei Huang ◽  
Mao Xiang Yi ◽  
Lin Wang ◽  
Hua Guo Liang
Keyword(s):  
Minimum Size ◽  
Application Time ◽  
Logical Circuit ◽  
Test Set ◽  
Test Cost ◽  
Test Application ◽  
Sharing Strategy ◽  
Data Volume ◽  
Set Sharing ◽  
Test Sets

A novel concurrent core test approach is proposed to reduce the test cost of SoC. Before test, a novel test set sharing strategy is proposed to obtain a minimum size of merged test set by merging the test sets corresponding to cores under test (CUT).Moreover, it can be used in conjunction with general compression/decompression techniques to further reduce test data volume (TDV). During test, the proposed vector separating device which is composed of a set of simple combinational logical circuit (CLC) is designed for separating the vector from the merged test set to the correspondent test core. This approach does not add any test vector for each core and can test synchronously to reduce test application time (TAT). Experimental results for ISCAS’ 89 benchmarks have been rproven the efficiency of the proposed approach.

Sign in / Sign up

Export Citation Format

Share Document