FORSA: Exploiting Filter Ordering to Reduce Switching Activity for Low Power CNNs

<div>Switching activity in digital circuits depends on the temporal distribution of the data participating in the operation which directly influences the interconnect, dynamic power and timing of the system. This paper proposes an efficient method for reducing both power and latency of matrix-multiplication operations found in many applications like convolution neural networks (CNNs). The approach takes advantage of the unique characterizes of CNN with input stationary for efficient multiply-add operation. Since most application use reduce accuracy for MAC, the proposed work assumed 8-bit fixed point representation. As a demonstrator, CIFAR-10 data set has been used for end to end analysis of the filters on a 3-ConV with 2-FC model structure. The filters’ were re-ordered to reduce the switching behaviour between successive weight fetching. This directly impacts the dynamic power consumption and miraculously makes the classification activity reduces cross-coupling capacitance which helps improve timing and noise.</div>

FORSA: Exploiting Filter Ordering to Reduce Switching Activity for Low Power CNNs

<div>Switching activity in digital circuits depends on the temporal distribution of the data participating in the operation which directly influences the interconnect, dynamic power and timing of the system. This paper proposes an efficient method for reducing both power and latency of matrix-multiplication operations found in many applications like convolution neural networks (CNNs). The approach takes advantage of the unique characterizes of CNN with input stationary for efficient multiply-add operation. Since most application use reduce accuracy for MAC, the proposed work assumed 8-bit fixed point representation. As a demonstrator, CIFAR-10 data set has been used for end to end analysis of the filters on a 3-ConV with 2-FC model structure. The filters’ were re-ordered to reduce the switching behaviour between successive weight fetching. This directly impacts the dynamic power consumption and miraculously makes the classification activity reduces cross-coupling capacitance which helps improve timing and noise.</div>

Logic Synthesis Strategy Oriented to Low Power Optimization

The article presents a synthesis strategy focused on low power implementations of combinatorial circuits in an array-type FPGA structure. Logic functions are described by means of BDD. A new form of the SWitch activity BDD diagram (SWBDD) is proposed, which enables a function decomposition to minimize the switching activity of circuits. The essence of the proposed idea lies in the proper ordering of the variables and cutting the diagram, ensuring the minimization of switching in the combination circuit. This article contains the results of experiments confirming the effectiveness of the developed concept of decomposition. They were performed on popular benchmarks using academic and commercial synthesis systems.

A Low Noise High Input Impedance Chopper-Stabilized Biopotential Amplifier with Ripple Reduction Technique

Biopotential signals are created as a result of the electrochemical activity of the many cells that comprise the nervous system, and they represent both normal and pathological organ function. These signals must be identified with extreme caution because they are surrounded by a great deal of noise when detected by sensors. This article explores a novel biopotential amplifier that incorporates the chopper stabilization technique to increase noise performance and minimize offset. However, by introducing the chopper modulator into the proposed design, the amplifier's overall input impedance was lowered, which was then increased to greater than 200 MΩ by adding the forward auxiliary path to the input branch. Additionally, the output ripple, produced due to switching activity and up-sampling, was reduced by inclusion of the R-C ripple removing block at the output of the operational transconductance amplifier (OTA). The designed architecture had a mid-band gain of 40dB with a power consumption of 9 µW and an offset of 10µV and a CMRR of 82 dB. It generated a noise of 42nV/√Hz. Also, the obtained results were compared with a conventional amplifier. The proposed design was verified by carrying out simulations using 180nm technology parameters. Cadence Virtuoso (Schematic editor), Spectre (Simulator), Symica and Magic (Layout) tools were used to complete the implementation and simulation of the proposed design. HIGHLIGHTS Biopotential signals are created as a result of the electrochemical activity of the many cells which must be identified with extreme caution because they are surrounded by a great deal of noise when detected by sensors It explores a novel biopotential amplifier that incorporates the chopper stabilization technique to increase noise performance and minimize offset By introducing the chopper modulator into the proposed design, the amplifier's overall input impedance was lowered, which was then increased to greater than 200 MΩ by adding the forward auxiliary path to the input branch The output ripple, produced due to switching activity and up-sampling, was reduced by inclusion of the R-C ripple removing block at the output of the operational transconductance amplifier (OTA) The designed architecture had a mid-band gain of 40dB with a power consumption of 9 µW and an offset of 10 µV and a CMRR of 82 dB. It generated a noise of 42 nV/√Hz GRAPHICAL ABSTRACT

CONCEALING-Gate: Optical Contactless Probing Resilient Design

Optical probing, though developed as silicon debugging tools from the chip backside, has shown its capability of extracting secret data, such as cryptographic keys and user identifications, from modern system-on-chip devices. Existing optical probing countermeasures are based on detecting any device modification attempt or abrupt change in operating conditions during asset extraction. These countermeasures usually require additional fabrication steps and cause area and power overheads. In this article, we propose a novel low-overhead design methodology to prevent optical probing. It leverages additional operational logic gates, termed as “CONCEALING-Gates,” inserted as neighbor gates of the logic gates connected to the nets carrying asset signals. The switching activity of the asset carrying logic is camouflaged with the switching activity of the concealing-gate. The input signal and placement in the layout of the concealing-gates must be selected in such a way that they remain equally effective in preventing different variants of optical probing, i.e., electro-optical frequency mapping and Electro-optical probing. The methodology is suitable for the existing ASIC/FPGA design flow and fabrication process, since designing new standard logic cells is not required. We have performed a comprehensive security evaluation of the concealing-gates using a security metric developed based on the parameters that are crucial for optical probing. The attack resiliency of the logic cells, protected by concealing-gates, is evaluated using an empirical study-based simulation methodology and experimental validation. Our analysis has shown that in the presence of concealing-gates, logic cells achieve high resiliency against optical contactless probing techniques.

Clock Gating Flip-Flop using Embedded XoR Circuitry

Flip flops/Pulsed latches are one of the main contributors of dynamic power consumption. In this paper, a novel flip-flop (FF) using clock gating circuitry with embedded XOR, GEMFF, is proposed. Using post layout simulation with 45nm technology, GEMFF outperforms prior stateof-the-art flip-flop by 25.1% at 10% data switching activity in terms of power consumption.