On-Chip Relative Single-Event Transient/Single- Event Upset Susceptibility Test Circuit for Integrated Circuits Working in Real Time

2018 ◽  
Vol 65 (1) ◽  
pp. 376-381 ◽  
Author(s):  
Peipei Hao ◽  
Shuming Chen ◽  
Zhenyu Wu ◽  
Yaqing Chi
2007 ◽  
Vol 54 (6) ◽  
pp. 2303-2311 ◽  
Author(s):  
P. E. Dodd ◽  
J. R. Schwank ◽  
M. R. Shaneyfelt ◽  
J. A. Felix ◽  
P. Paillet ◽  
...  

1987 ◽  
Vol 34 (6) ◽  
pp. 1310-1315 ◽  
Author(s):  
J. A. Zoutendyk ◽  
H. R. Schwartz ◽  
R. K. Watson ◽  
Z. Hasnain ◽  
L. R. Nevill

2006 ◽  
Vol 6 (4) ◽  
pp. 542-549 ◽  
Author(s):  
Balaji Narasimham ◽  
Vishwa Ramachandran ◽  
Bharat L. Bhuva ◽  
Ronald D. Schrimpf ◽  
Arthur F. Witulski ◽  
...  

2012 ◽  
Vol 198-199 ◽  
pp. 1105-1109
Author(s):  
Xin Jie Zhou ◽  
Jing He Wei ◽  
Lei Lei Li

As wide application of EEPROM devices in space and military field, more and more researches focus on its radiation hardened characteristics in international. To improve the single-event effect (SEE) tolerant ability of read-out circuits in the memory, a radiation hardened circuit is designed. The design kernels of radiation hardened latch-flip are given and designed to resist the single-event upset (SEU) effect. A correction circuit is proposed to resist the single-event transient (SET) effect. The performances of this design are: SEU (LET)th ≥ 27 MeV•cm2/mg, SEL(LET)th ≥ 75 MeV•cm2/mg , read out time ≤200 ns. The new design not only satisfied the needs of present work, but supplies a worthful reference for radiation hardened circuit design in future.


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