A Multilayer Process for the Connection of Fine-Pitch-Devices on Molded Interconnect Devices (MIDs)

2008 ◽  
Author(s):  
Thomas Leneke ◽  
Soeren Hirsch ◽  
Bertram Schmidt
Keyword(s):  
Flip Chip ◽  
Three Dimensional ◽  
Area Array ◽  
Fine Pitch ◽  
Key Factor ◽  
Functional Features ◽  
Escape Routing ◽  
Electrical Connections ◽  
Molded Interconnect Devices ◽  
Metallization Process

A key factor for the propagation of technological applications is the miniaturization of respective components, subsystems and overall systems. To meet future requirements in such size decreasing environments the packaging and mounting technology needs new impulses. 3D-MIDs (three-dimensional molded interconnect devices) exhibit a high potential for smart packages and assemblies. A three-dimensional shaped circuit carrier allows the integration of various functional features (e.g. electrical connections, housing, thermal management, mechanical support). This combination makes a further system shrinking possible. Yet, the mounting of high-density area-array fine-pitch packaged semiconductors (BGA, CSP, MCM) or bare dies to 3D-MIDs is problematic. The lack of a three-dimensional multilayer technology makes a collision free escape routing for devices with a high I/O count difficult. Therefore a new 3D-MID multilayer process was developed and combined with an established 3D-MID metallization process. A demonstrator with three metallization layers, capable, e.g., for flip-chip mounting of area-array packages, is fabricated. The multilayer structure of the demonstrator is investigated with respect to the mechanical and electrical behavior.

scholarly journals Flexible free-standing SU-8 microfluidic impedance spectroscopy sensor for 3-D molded interconnect devices application

2016 ◽  
Vol 5 (1) ◽  
pp. 55-61 ◽  
Author(s):  
Marc-Peter Schmidt ◽  
Aleksandr Oseev ◽  
Christian Engel ◽  
Andreas Brose ◽  
Bertram Schmidt ◽  
...  
Keyword(s):  
Impedance Spectroscopy ◽  
Flip Chip ◽  
Three Dimensional ◽  
Impedance Spectrum ◽  
Fabrication Technology ◽  
Free Standing ◽  
Flexible Polymer ◽  
Opposite Electrode ◽  
Electrical Connections ◽  
Molded Interconnect Devices

Abstract. The current contribution reports about the fabrication technology for the development of novel microfluidic impedance spectroscopy sensors that are directly attachable on 3-D molded interconnect devices (3D-MID) that provides an opportunity to create reduced-scale sensor devices for 3-D applications. Advantages of the MID technology in particular for an automotive industry application were recently discussed (Moser and Krause, 2006). An ability to integrate electrical and fluidic parts into the 3D-MID platform brings a sensor device to a new level of the miniaturization. The demonstrated sensor is made of a flexible polymer material featuring a system of electrodes that are structured on and embedded in the SU-8 polymer. The sensor chips can be directly soldered on the MID due to the electroless plated contact pads. A flip chip process based on the opposite electrode design and the implementation of all fluidic and electrical connections at one side of the sensors can be used to assemble the sensor to a three-dimensional substrate. The developed microfluidic sensor demonstrated a predictable impedance spectrum behavior and a sufficient sensitivity to the concentration of ethanol in deionized water. To the best of our knowledge, there is no report regarding such sensor fabrication technology.

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000708-000735 ◽  
Author(s):  
Zhaozhi Li ◽  
John L. Evans ◽  
Paul N. Houston ◽  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
High Yield ◽  
Process Time ◽  
Assembly Process ◽  
Wafer Level ◽  
Fine Pitch

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

Microbump Processing for 3D IC Integration

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 001028-001049
Author(s):  
Feng Li ◽  
Andrew W. Owens ◽  
Qianyi Li
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Bonding Process ◽  
Replication Process ◽  
Spatial Efficiency ◽  
Bonding Structure ◽  
Fine Pitch ◽  
Bonding Method ◽  
Self Replication

In recent years, the development of microbumps has allowed even smaller sizes of ICs to utilize the flip chip technique. In addition, microbumps have enabled the implementation of three-dimensional (3D) ICs, which drastically improve the spatial efficiency of packaging. However, as the bumps size decreases and the number increases, several process challenges must be considered, for example, the height consistency of bump, the ratio of miss and deformity bump and the yield and strength of interconnection, etc. Therefore, it is increasingly important to study the interconnection technology and materials of high-density microbump interconnection. After briefly introducing the common electronic packaging techniques, including wire bonding, tape-automated bonding and flip chip, this paper reviews microbumps as an advanced bonding technology. Techniques such as Controlled Collapse Chip Connection - New Process(C4NP), printing, insert bump bonding, and self-replication process are discussed and compared. C4NP can achieve low-cost, fine pitch bumping by utilizing varied lead-free solder alloys, which overcomes the limitation of existing bumping technologies. Depending on the microbump size, engraved mask stump, and photosensitive organic mask and squeegee are the two ways for micro-bump printing. The micro-insert bump bonding process is new to stack chips vertically, which has robust bonding structure and a simpler bonding process compared to Cu pillar bonding process. The self-replication process is using the surface tension property of molten solder between the micro bridged bump to get two bumps with same volume and geometries on each faced pairs of lands. The use of two common material for the microbump, Cu, Sn, and its alloys are presented along with the differences in the process for each. As with any technology, a new breakthrough addressing an issue brings with it its own set of shortfalls. Microbumps are no different. The various techniques and materials used to realize the reduced scale bonding method are subject to a number of challenges. Most prominent among them are electromigration, thermomigration, and thermallyinduced mechanical fatigue, which are discussed in this paper.

Anisotropic conductive film for fine-pitch interconnects

2016 ◽  
Vol 2016 (1) ◽  
pp. 000044-000049 ◽  
Author(s):  
Daniel Nilsen Wright ◽  
Branson D. Belle ◽  
Kari Schjølberg-Henriksen ◽  
Hoang-Vu Nguyen ◽  
Jakob Gakkestad ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Mechanisms ◽  
Anisotropic Conductive Film ◽  
Environmental Testing ◽  
Fine Pitch ◽  
Conductive Film ◽  
The Stability ◽  
Mechanical Bonds ◽  
Electrical Connections

Abstract An anisotropic conductive film (ACF) can be utilized to simultaneously form mechanical bonds and electrical connections during flip-chip assembly. The electrical connection is created by trapping randomly dispersed metallized polymer spheres (MPS) in the ACF that are deformed during the bonding process. This work postulates that the reliability of interconnects formed with ACF depends on the degree to which the MPS are deformed. Silicon samples with fine-pitch electrical test structures were flip-chip assembled using an ACF and measured in-situ during environmental testing. Interconnects with MPS deformation below 60% proved more stable than interconnects with higher deformation during exposure to 85% relative humidity at 20 °C, 45 °C, 60 °C and 85 °C, as postulated. On the other hand, the stability of the interconnects did not show a dependence on MPS deformation during exposure to thermal shock cycling (TSC) (−55 °C / +125 °C, 7 s transit time, 700 cycles). The results suggest that deformation of MPS is a central factor with respect to reliability of ACF-bonded fine-pitch samples exposed to humid conditions, but the results also indicate that other failure mechanisms are more important for samples exposed to thermally unstable conditions.

Assembly Process Development for Fine Pitch Flip Chip Silicon-to-Silicon 3D Wafer Level Integration with No Flow Underfill

2010 ◽  
Vol 7 (3) ◽  
pp. 146-151 ◽  
Author(s):  
Zhaozhi Li ◽  
Sangil Lee ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
3D Packaging ◽  
Small Form Factor

The industry has witnessed the adoption of the flip chip for its low cost, small form factor, high performance, and great I/O flexibility. As three-dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon-to-silicon assembly, is gaining more and more popularity. No flow underfill is of special interest for the wafer level flip chip assembly, as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would otherwise be necessary for the standard capillary underfill process. This paper introduces the development of a no flow underfill process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underfill reflow profile study, underfill dispense amount study, chip floating control, underfill voiding reduction, and yield improvement. Also, different no flow underfill candidates were investigated to determine the best performing processing material.

Three-Dimensional Thermomechanical Simulation of Fine-Pitch High-Count Ball Grid Array Flip-Chip Assemblies

2013 ◽  
Vol 43 (3) ◽  
pp. 671-684 ◽  
Author(s):  
W. Kpobie ◽  
N. Bonfoh ◽  
C. Dreistadt ◽  
M. Fendler ◽  
P. Lipinski
Keyword(s):  
Flip Chip ◽  
Three Dimensional ◽  
Ball Grid Array ◽  
High Count ◽  
Fine Pitch ◽  
Thermomechanical Simulation

TCB Process Options to Achieve the Lowest Cost

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001277-001301
Author(s):  
Tom Strothmann
Keyword(s):  
Flip Chip ◽  
Bonding Process ◽  
Heating Rates ◽  
Fine Pitch ◽  
Key Factor ◽  
3D Assembly ◽  
Cost Calculations ◽  
Improved Performance ◽  
Memory Applications ◽  
The Cost

Thermocompression bonding enables the next generation fine pitch, 2.5D and 3D assembly technologies using Cu pillar interconnects, but to achieve widespread adoption the cost of TCB must become competitive with mass reflow processes. Stacked memory products drive the commercial volume today using TSV structures and TCB since it is the only technology able to achieve the desired stacked die construction and improved performance, but reducing the cost of assembly is still a key goal for those suppliers. In non-memory applications the choice of TCB can be driven by the bump pitch of the device or the requirement to control warpage of large die on laminate during assembly, but cost is still a key factor in the decision. The cost of a TCB process is largely driven by the UPH of the process where cost calculations are based on the cost per unit of material produced. As the UPH of a TCB process approaches 1400, the differential cost of the TCB process as compared to mass reflow becomes negligible. In the choice of a potential TCB process, special attention must be given to those processes that enable the highest UPH and the lowest cost. Processes used for TCB today can be grouped into two main categories; processes that use a pre-applied underfill and those that apply underfill after the bonding process. Underfills applied prior to bonding can be in the form of a non-conductive paste (TC-NCP) applied to a substrate or a non-conductive film applied to the wafer before dicing (TC-NCF). If underfill is applied after the bonding process, it is done as a Capillary Underfill (TC-CUF). In this case the die is underfilled in much the same way as in standard flip chip processes, but the process can be more challenging because of flux cleaning requirements and the narrower bondline of a typical TCB device. UPH is primarily driven by two factors; the range of temperature required by the bond head and the temperature ramp rate of the bond head. A process with less temperature range will have higher UPH and bond heads designed for the fastest cooling and heating rates will provide higher UPH processes. Two process options have been developed to minimize the temperature excursions required by the bond head and maximize the throughput. TC- NCF processes targeting stacked die and interposer products have been developed with throughputs approaching 2000 UPH. Substrate flux TC-CUF processes targeting assembly on laminate have been developed with throughputs that approach 2500 UPH. These two processes are expected to dominate TCB volume production moving forward as TCB enters mainstream production. This presentation will describe the methods used to achieve high throughput for both processes and the product application space appropriate for each one.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

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