Microbump Processing for 3D IC Integration

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 001028-001049
Author(s):  
Feng Li ◽  
Andrew W. Owens ◽  
Qianyi Li
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Bonding Process ◽  
Replication Process ◽  
Spatial Efficiency ◽  
Bonding Structure ◽  
Fine Pitch ◽  
Bonding Method ◽  
Self Replication

In recent years, the development of microbumps has allowed even smaller sizes of ICs to utilize the flip chip technique. In addition, microbumps have enabled the implementation of three-dimensional (3D) ICs, which drastically improve the spatial efficiency of packaging. However, as the bumps size decreases and the number increases, several process challenges must be considered, for example, the height consistency of bump, the ratio of miss and deformity bump and the yield and strength of interconnection, etc. Therefore, it is increasingly important to study the interconnection technology and materials of high-density microbump interconnection. After briefly introducing the common electronic packaging techniques, including wire bonding, tape-automated bonding and flip chip, this paper reviews microbumps as an advanced bonding technology. Techniques such as Controlled Collapse Chip Connection - New Process(C4NP), printing, insert bump bonding, and self-replication process are discussed and compared. C4NP can achieve low-cost, fine pitch bumping by utilizing varied lead-free solder alloys, which overcomes the limitation of existing bumping technologies. Depending on the microbump size, engraved mask stump, and photosensitive organic mask and squeegee are the two ways for micro-bump printing. The micro-insert bump bonding process is new to stack chips vertically, which has robust bonding structure and a simpler bonding process compared to Cu pillar bonding process. The self-replication process is using the surface tension property of molten solder between the micro bridged bump to get two bumps with same volume and geometries on each faced pairs of lands. The use of two common material for the microbump, Cu, Sn, and its alloys are presented along with the differences in the process for each. As with any technology, a new breakthrough addressing an issue brings with it its own set of shortfalls. Microbumps are no different. The various techniques and materials used to realize the reduced scale bonding method are subject to a number of challenges. Most prominent among them are electromigration, thermomigration, and thermallyinduced mechanical fatigue, which are discussed in this paper.

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

No Flow Underfill Process Development for Fine Pitch Flip Chip Silicon to Silicon Wafer Level Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000708-000735 ◽  
Author(s):  
Zhaozhi Li ◽  
John L. Evans ◽  
Paul N. Houston ◽  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
High Yield ◽  
Process Time ◽  
Assembly Process ◽  
Wafer Level ◽  
Fine Pitch

The industry has witnessed the adoption of flip chip for its low cost, small form factor, high performance and great I/O flexibility. As the Three Dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon to silicon assembly, is gaining more and more popularity. Most flip chip packages require underfill to overcome the CTE mismatch between the die and substrate. Although the flip chip to wafer assembly is a silicon to silicon integration, the underfill is necessary to overcome the Z-axis thermal expansion as well as the mechanical impact stresses that occur during shipping and handling. No flow underfill is of special interest for the wafer level flip chip assembly as it can dramatically reduce the process time as well as bring down the average package cost since there is a reduction in the number of process steps and the dispenser and cure oven that would be necessary for the standard capillary underfill process. Chip floating and underfill outgassing are the most problematic issues that are associated with no flow underfill applications. The chip floating is normally associated with the size/thickness of the die and volume of the underfill dispensed. The outgassing of the no flow underfill is often induced by the reflow profile used to form the solder joint. In this paper, both issues will be addressed. A very thin, fine pitch flip chip and 2x2 Wafer Level CSP tiles are used to mimic the assembly process at the wafer level. A chip floating model will be developed in this application to understand the chip floating mechanism and define the optimal no flow underfill volume needed for the process. Different reflow profiles will be studied to reduce the underfill voiding as well as improve the processing yield. The no flow assembly process developed in this paper will help the industry understand better the chip floating and voiding issues regarding the no flow underfill applications. A stable, high yield, fine pitch flip chip no flow underfill assembly process that will be developed will be a very promising wafer level assembly technique in terms of reducing the assembly cost and improving the throughput.

Assembly Process Development for Fine Pitch Flip Chip Silicon-to-Silicon 3D Wafer Level Integration with No Flow Underfill

2010 ◽  
Vol 7 (3) ◽  
pp. 146-151 ◽  
Author(s):  
Zhaozhi Li ◽  
Sangil Lee ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
...  
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Process Development ◽  
Low Cost ◽  
Three Dimensional ◽  
Process Time ◽  
Wafer Level ◽  
Fine Pitch ◽  
3D Packaging ◽  
Small Form Factor

The industry has witnessed the adoption of the flip chip for its low cost, small form factor, high performance, and great I/O flexibility. As three-dimensional (3D) packaging technology moves to the forefront, the flip chip to wafer integration, which is also a silicon-to-silicon assembly, is gaining more and more popularity. No flow underfill is of special interest for the wafer level flip chip assembly, as it can dramatically reduce the process time and the cost per package, due to the reduction in the number of process steps as well as the dispenser and cure oven that would otherwise be necessary for the standard capillary underfill process. This paper introduces the development of a no flow underfill process for a sub-100 micron pitch flip chip to CSP wafer level assembly. Challenges addressed include the no flow underfill reflow profile study, underfill dispense amount study, chip floating control, underfill voiding reduction, and yield improvement. Also, different no flow underfill candidates were investigated to determine the best performing processing material.

Advancements in Flip Chip Assembly Equipment and Processes

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001328-001358 ◽  
Author(s):  
Bob Chylak ◽  
Horst Clauberg ◽  
Daniel Buergi
Keyword(s):  
Flip Chip ◽  
First Generation ◽  
Standard Process ◽  
Productivity Improvement ◽  
Gate Arrays ◽  
Fine Pitch ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Pros And Cons ◽  
Bonding Method

High I/O devices such as microprocessors, applications processors and field programmable gate arrays have transitioned from wire bonding to flip chip interconnect as the I/O densities have increased above 2000. As the bump pitch shrinks the standard process flow for production flip chip processes is challenged. As the bump pitch continues to shrink the accuracy of standard flip chip bonders is not adequate for the fine pitch packages of tomorrow. The options to resolve this issue are extending the accuracy for standard flip chip bonders or moving the assembly of these packages to the inherently more accurate thermo-compression bonders. This paper will discuss the pros and cons of each approach along with showing data which indicates what accuracies are actually required. Although substrate manufacturers have developed low CTE designs which mitigate the warpage caused by the mismatch between the Si die and the substrate as the assembled package travels through the reflow oven, warpage at finer pitches is becoming more and more difficult to control in flip chip processes. Thermocompression (TC) bonding is seen as the next-generation packaging technology that will resolve this issue through local reflow of the solder and elimination of the reflow oven. Despite the tremendous technical and quality advantages of TC bonding, adoption has been limited by the relatively low throughput of the first generation thermocompression bonders. In this paper we describe bonding results obtained with an innovative flip chip bonding method to optimize the process to dramatically improve the throughput by applying flux directly to the substrate rather than dipping the pillars in a bath. A study of this process and comparison of various methods of accomplishing it along with their related costs are discussed in the paper. A second large productivity improvement that is promising by eliminating the need for cooling the die before transferring die that has pre-applied underfill film laminated to it is also studied with productivity models developed. Finally a unique equipment concept for managing the transition from mass reflow to thermo-compression bonding will be presented.

Thermally Activated Bumping Process using Sn3.0Ag0.5Cu Solder Powder for Low-Cost Interposers

2013 ◽  
Vol 2013 (1) ◽  
pp. 000420-000423
Author(s):  
Kwang-Seong Choi ◽  
Ho-Eun Bae ◽  
Haksun Lee ◽  
Hyun-Cheol Bae ◽  
Yong-Sung Eom
Keyword(s):  
Screen Printing ◽  
Flip Chip ◽  
Solder Bump ◽  
Low Cost ◽  
Organic Substrate ◽  
Lead Free ◽  
Lead Free Solder ◽  
Thermally Activated ◽  
Fine Pitch ◽  
Free Solder

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process with the result that a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology can be easily implemented. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 μm is, successfully, formed.

Stress Analysis under Cu Bump Bonding Process

2012 ◽  
Vol 217-219 ◽  
pp. 2317-2321 ◽  
Author(s):  
Chun Yue Huang ◽  
Ying Liang ◽  
Song Wu ◽  
Tian Ming Li
Keyword(s):  
Stress Distribution ◽  
Flip Chip ◽  
Mechanical Performance ◽  
Copper Wire ◽  
Low Cost ◽  
Element Model ◽  
Bonding Process ◽  
Bonding Pressure ◽  
Shaping Process ◽  
Set Up

The copper wire has some advantages in thermal performance, mechanical performance, and low cost, which make it can provide the lowest cost flip-chip(FC) package for low I/O density device. The 2D Cu stud bump finite element model was set up by using ANSYS/LS-DYNA with LOLID162 element to dynamic simulate the Cu stud bump bonding shaping process. The stress distribution in the Cu stud bump and the pad during the bonding process were studied, and the influence of pad thickness on the stress distribution of Si chip was also analyzed. The results shows that under the bonding process the Cu bump height is mainly influenced by the bonding pressure and the top shape of the Cu bump is influenced by ultrasonic energy, the increase of pad thickness results in reducing stress concentration inside the Si chip.

A Multilayer Process for the Connection of Fine-Pitch-Devices on Molded Interconnect Devices (MIDs)

2008 ◽  
Author(s):  
Thomas Leneke ◽  
Soeren Hirsch ◽  
Bertram Schmidt
Keyword(s):  
Flip Chip ◽  
Three Dimensional ◽  
Area Array ◽  
Fine Pitch ◽  
Key Factor ◽  
Functional Features ◽  
Escape Routing ◽  
Electrical Connections ◽  
Molded Interconnect Devices ◽  
Metallization Process

A key factor for the propagation of technological applications is the miniaturization of respective components, subsystems and overall systems. To meet future requirements in such size decreasing environments the packaging and mounting technology needs new impulses. 3D-MIDs (three-dimensional molded interconnect devices) exhibit a high potential for smart packages and assemblies. A three-dimensional shaped circuit carrier allows the integration of various functional features (e.g. electrical connections, housing, thermal management, mechanical support). This combination makes a further system shrinking possible. Yet, the mounting of high-density area-array fine-pitch packaged semiconductors (BGA, CSP, MCM) or bare dies to 3D-MIDs is problematic. The lack of a three-dimensional multilayer technology makes a collision free escape routing for devices with a high I/O count difficult. Therefore a new 3D-MID multilayer process was developed and combined with an established 3D-MID metallization process. A demonstrator with three metallization layers, capable, e.g., for flip-chip mounting of area-array packages, is fabricated. The multilayer structure of the demonstrator is investigated with respect to the mechanical and electrical behavior.

Advanced Substrate Applied Fluxing Underfill for Bonding of Fine Pitch Solder Capped Cu Pillars to Oxidized Cu Substrates

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 000924-000943
Author(s):  
Russell Stapleton ◽  
Jim Greig
Keyword(s):  
Cross Sections ◽  
Flip Chip ◽  
Low Cost ◽  
Cost Effective ◽  
Filler Loading ◽  
Thermal Compression ◽  
Transparent Substrate ◽  
Fine Pitch ◽  
Before And After ◽  
Cu Substrates

Underfill solutions for fine pitch flip chip assemblies is an active area of development. Non-conductive films (NCF) and pastes (NCP) have shown great potential in bridging the gap between no-flow and capillary underfills for improving the reliability of fine pitched devices. But NCFs and NCPs require costly passivated pad finishes (e.g. Au, Sn, Ni, OSP) or careful substrate handling for proper solder joint formation. In this paper, we will describe a new class of underfill material that benefits from the growing trend of using thermal compression bonding as a cost effective alternative to mass reflow based underfilling processes (e.g. capillary and no-flow). This material is a fluxing NCP that is useful for a wide variety of fine pitch substrates, including low cost Cu. The material we will demonstrate contains many advanced features: high filler loading, strong flux activity, long work life, off-tool pre-dispense, low stress, high Tg, high modulus and rapid cure. The all-in-one underfill demonstrated in this paper is applied by using a screen printing process, where the material is applied to all of the chip sites in one step achieving excellent application efficiency and wetting/conformity to the substrate. The substrate is glass, containing a 4x4 array of die sites. Each of the die sites are 5x5mm in size with a full area array of 2501 Cu pads (50um pads on 100um pitch) that are pre-oxidized for 1h at 175C in air prior to printing (to simulate a dehydration bake). This transparent substrate was chosen to show the robust nature of the underfill for fluxing, stability and void-free placement/cure. Images of the substrate, before and after chip bonding will be given, along with cross sections. Details of the material properties will also be discussed.

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