A GaAs monolithic amplifier with extremely low power consumption

1991 ◽  
Vol 69 (3-4) ◽  
pp. 177-179
Author(s):  
Langis Roy ◽  
Malcolm G. Stubbs ◽  
James S. Wight
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Gain ◽  
Low Power Consumption ◽  
Monolithic Microwave Integrated Circuit ◽  
Dc Power ◽  
Broadband Amplifier ◽  
Effect Transistor ◽  
And Performance

The design and performance of a high-gain, monolithic, broadband amplifier with extremely low power consumption are described. The amplifier, fabricated using a 0.5 μm GaAs depletion-mode MESFET (metal semiconductor field effect transistor) process, utilizes very small gate width devices to achieve a measured gain of 19 dB and a 0.1 to 2.1 GHz bandwidth with only 63 mW dc power dissipation. This is the lowest power consumption broadband MMIC (monolithic microwave integrated circuit) reported to date and is intended for mobile radio applications.

Flexible low-power source-gated transistors with solution-processed metal–oxide semiconductors

Nanoscale ◽  
2020 ◽  
Vol 12 (42) ◽  
pp. 21610-21616
Author(s):  
Dingwei Li ◽  
Momo Zhao ◽  
Kun Liang ◽  
Huihui Ren ◽  
Quantan Wu ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Power Consumption ◽  
Low Power ◽  
High Gain ◽  
Power Source ◽  
Metal Oxide Semiconductors ◽  
Low Power Consumption ◽  
Light Weight ◽  
Solution Processed ◽  
Oxide Semiconductors

Flexible light weight In2O3-based source-gated transistors are achieved with high gain, fast saturation and low power consumption.

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

A novel indirect read technique based SRAM with ability to charge recycle and differential read for low power consumption, high stability and performance

2020 ◽  
Vol 97 ◽  
pp. 104723 ◽  
Author(s):  
Debasish Nayak ◽  
Prakash Kumar Rout ◽  
Sudhakar Sahu ◽  
Debiprasad Priyabrata Acharya ◽  
Umakanta Nanda ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Stability ◽  
Low Power Consumption ◽  
And Performance
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