A Low-Power, High-Gain, and Low-Noise 802.11a Down-Conversion Mixer in 0.35-μm SiGe Bi-CMOS Technology

2017 ◽  
Vol 26 (09) ◽  
pp. 1750134 ◽  
Author(s):  
Jun-Da Chen ◽  
Song-Hao Wang
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Conversion Gain ◽  
Dc Power ◽  
Down Conversion

The paper presents a novel 5.15[Formula: see text]GHz–5.825[Formula: see text]GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-[Formula: see text]m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843[Formula: see text]mm2. The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14[Formula: see text]dB power conversion gain, [Formula: see text]6[Formula: see text]dBm input third-order intercept point (IIP3), 6.85[Formula: see text]dB double side band (DSB) noise figure. The total mixer current is about 1.54[Formula: see text]mA from 1.4[Formula: see text]V supply voltage including output buffer. The total dc power consumption is 2.15[Formula: see text]mW.

scholarly journals 0.5-7.5 GHZ LOW-POWER, INDUCTORLESS CURRENT FOLDED MIXER IN 0.18-μM CMOS FOR BROADBAND APPLICATIONS

2013 ◽  
pp. 112-116
Author(s):  
ZAHRA GHANE FASHTALI ◽  
MAHROKH MAGHSOODI ◽  
REZA EBRAHIMI ATANI ◽  
MEHRGAN MAHDAVI
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Noise Figure ◽  
Cmos Process ◽  
Conversion Gain ◽  
Fully Differential ◽  
Dc Power ◽  
Maximum Conversion ◽  
Cell Topology ◽  
Down Conversion

A fully differential low-power down-conversion mixer using a TSMC 0.18-μm CMOS process is presented in this paper. The proposed mixer is based on a folded double-balanced Gilbert cell topology that enhances conversion gain and reduces power dissipation. Though, this mixer is designed for 5.8 GHz ISM band applications, but at 0.5-7.5 GHz, the proposed mixer exhibits a maximum conversion gain of 12dB, maximum IIP3 of -2.5 dBm, maximum input 1-dB compression point of -13 dBm, the minimum DSB noise figure of 9.2 dB and a dc power consumption of 2.52 mW at 1.8 V power supply. Also, this circuit architecture increases port-to-port isolations to above 140 dB. Moreover this mixer is suitable for broadband applications.

scholarly journals A 60 GHz fully differential LNA in 90 nm CMOS technology

2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transmission Lines ◽  
Noise Figure ◽  
Design Procedure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
60 Ghz ◽  
Fully Differential

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.

Optimized Design of Low Power Complementary Metal Oxide Semiconductor Low Noise Amplifier for Zigbee Application

2021 ◽  
Vol 18 (4) ◽  
pp. 1327-1330
Author(s):  
S. Manjula ◽  
R. Karthikeyan ◽  
S. Karthick ◽  
N. Logesh ◽  
M. Logeshkumar
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Design System ◽  
Cmos Process ◽  
Design Specifications ◽  
Noise Amplifier

An optimized high gain low power low noise amplifier (LNA) is presented using 90 nm CMOS process at 2.4 GHz frequency for Zigbee applications. For achieving desired design specifications, the LNA is optimized by particle swarm optimization (PSO). The PSO is successfully implemented for optimizing noise figure (NF) when satisfying all the design specifications such as gain, power dissipation, linearity and stability. PSO algorithm is developed in MATLAB to optimize the LNA parameters. The LNA with optimized parameters is simulated using Advanced Design System (ADS) Simulator. The LNA with optimized parameters produces 21.470 dB of voltage gain, 1.031 dB of noise figure at 1.02 mW power consumption with 1.2 V supply voltage. The comparison of designed LNA with and without PSO proves that the optimization improves the LNA results while satisfying all the design constraints.

scholarly journals A Low-Noise, High-Gain, and Small-Size UWB Mixer Utilizing Negative Impedance Technique and Source Input Method

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2655
Author(s):  
Zhaokun Zhou ◽  
Xiaoran Li ◽  
Xinghua Wang ◽  
Wei Gu
Keyword(s):  
Flicker Noise ◽  
Noise Figure ◽  
Supply Voltage ◽  
High Gain ◽  
Low Noise ◽  
Ultra Wideband ◽  
Conversion Gain ◽  
Chip Area ◽  
Input Method ◽  
Impedance Technique

This paper presents an ultra-wideband (UWB) down-conversion mixer with low-noise, high-gain and small-size. The negative impedance technique and source input method are applied for the proposed mixer. The negative impedance achieves the dynamic current injection and increases the mixer output impedance, which reduces the mixer flicker noise and increases its conversion gain. The source input method allows the input matching networks to be cancelled, avoiding the noise and loss introduced by the matching resistors, saving the chip area occupied by the matching inductors. The proposed mixer is designed in 45-nm SOI process provided by GlobalFoundries. The simulation results show a conversion gain of 11.4–14.3 dB, ranging from 3.1 to 10.6 GHz, a minimum noise figure of 9.8 dB, a RF port return loss of less than −11 dB, a port-to-port isolation of better than −48 dB, and a core chip area of 0.16 × 0.16 mm2. The power consumption from a 1 V supply voltage is 2.85 mW.

scholarly journals A concurrent dual-band CMOS low noise amplifier at 2.4/5.2 GHz for WLAN applications

2019 ◽  
Vol 14 (2) ◽  
pp. 555
Author(s):  
S.A.Z. Murad ◽  
A. F. Hasan ◽  
A. Azizan ◽  
A. Harun ◽  
J. Karim
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Notch Filter ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Dual Band ◽  
Common Source ◽  
Noise Amplifier

<span>This paper presents a concurrent dual-band CMOS low noise amplifier (LNA) at operating frequency of 2.4 GHz and 5.2 GHz for WLAN applications. The proposed LNA employed cascode common source to obtain high gain using 0.13-µm CMOS technology. The concurrent dual-band frequencies are matched using LC network band-pass and band-stop notch filter at the input and output stages. The filters help to shape the frequency response of the proposed LNA. The simulation results indicate that the LNA achieves a forward gain of 21.8 dB and 14.22 dB, input return loss of -18 dB and -14 dB at 2.4 GHz and 5.2 GHz, respectively. The noise figure of 4.1 dB and 3.5 dB with the input third-order intercept points 7 dBm and 10 dBm are obtained at 2.4 GHz and 5.2 GHz, respectively. The LNA dissipates 2.4 mW power at 1.2 V supply voltage with a chip size of 1.69 mm2.</span>

scholarly journals A Low-Noise Amplifier Utilizing Current-Reuse Technique and Active Shunt Feedback for MedRadio Band Applications

2020 ◽  
pp. 306-316
Author(s):  
Mutanizam Abdul Mubin ◽  
◽  
Arjuna Marzuki
Keyword(s):  
Low Power ◽  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Cmos Process ◽  
Current Reuse ◽  
Noise Amplifier

In this work, a low-power 0.18-μm CMOS low-noise amplifier (LNA) for MedRadio applications has been designed and verified. Cadence IC5 software with Silterra’s C18G CMOS Process Design Kit were used for all design and simulation work. This LNA utilizes complementary common-source current-reuse topology and subthreshold biasing to achieve low-power operation with simultaneous high gain and low noise figure. An active shunt feedback circuit is used as input matching network to provide a suitable input return loss. For test and measurement purpose, an output buffer was designed and integrated with this LNA. Inductorless design approach of this LNA, together with the use of MOSCAPs as capacitors, help to minimize the die size. On post-layout simulations with LNA die area of 0.06 mm2 and simulated total DC power consumption of 0.5 mW, all targeted specifications are met. The simulated gain, input return loss and noise figure of this LNA are 16.3 dB, 10.1 dB and 4.9 dB respectively throughout the MedRadio frequency range. For linearity, the simulated input-referred P1dB of this LNA is -26.7 dBm while its simulated IIP3 is -18.6 dBm. Overall, the post-layout simulated performance of this proposed LNA is fairly comparable to some current state-of-the-art LNAs for MedRadio applications. The small die area of this proposed LNA is a significant improvement in comparison to those of the previously reported MedRadio LNAs.

scholarly journals Design of a LNA in the frequency band 1.8-2.2GHz in 0.13μm CMOS Technology

2005 ◽  
Vol 3 ◽  
pp. 299-303
Author(s):  
E. Di Gioia ◽  
C. Hermann ◽  
H. Klar
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Low Cost ◽  
Operating Mode ◽  
Cmos Technology ◽  
Digital Circuit ◽  
High Gain ◽  
Low Noise ◽  
Noise Amplifier ◽  
Low Supply Voltage

Abstract. The subject of this work is a low noise amplifier (LNA), operating in the frequency range 1.8-2.1GHz. The CMOS 0.13μm technology is used in respect to the low cost of the final device. Among the specifications, a variable gain and an adjustable working frequency are required. In particular, four different working modes are provided: 1.8, 1.9 and 2.1GHz high gain and 2.1GHz low gain. The amplifier is designed to be used as first stage of a receiver for mobile telephony. For this reason low power consumption is taken into consideration (low supply voltage and low drain currents). A simple digital circuit, integrated on-chip, is used to select the operating mode of the LNA by means of two input pins. A Noise figure of 1dB is obtained with a supply voltage of 0.8V.

scholarly journals A Novel High Linearity and Low Power Folded CMOS LNA for UWB Receivers

2017 ◽  
Vol 27 (03) ◽  
pp. 1850047
Author(s):  
Xin Zhang ◽  
Chunhua Wang ◽  
Yichuang Sun ◽  
Haijun Peng
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Low Noise ◽  
Ultra Wideband ◽  
Oxide Semiconductor ◽  
High Linearity ◽  
Low Supply Voltage

This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18[Formula: see text][Formula: see text]m Complementary Metal-Oxide-Semiconductor (CMOS) technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8[Formula: see text]dB. The input and output reflection coefficients both are lower than [Formula: see text][Formula: see text]dB over 2.5–11.5[Formula: see text]GHz. The input third-order intercept point (IIP3) is 5.6[Formula: see text]dBm at 8[Formula: see text]GHz and the noise figure (NF) is lower than 4.0[Formula: see text]dB. The LNA consumes 5.4[Formula: see text]mW power under a 1[Formula: see text]V supply voltage.

A Low Power High Gain CMOS LNA with Multiple-Feedback Network for Low Voltage UWB Receiver

2016 ◽  
Vol 25 (06) ◽  
pp. 1650051 ◽  
Author(s):  
Lv Zhao ◽  
Chunhua Wang
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Low Noise ◽  
Common Source ◽  
Cmos Process ◽  
Chip Area ◽  
Feedback Network ◽  
Uwb Receiver

In this paper, a high gain low voltage low power Complementary Metal Oxide Semiconductor (CMOS) Low-noise Amplifier (LNA) using Chartered 0.18[Formula: see text][Formula: see text]m CMOS process for Ultra-wideband (UWB) receiver applications is presented. A novel multiple-feedback network constructed by the shunt feedback resistor with a transformer is adopted to realize desirable bandwidth extension and less chip area occupation in the common-source stage. All the cascaded transistors are configured by current-reuse structure and adjusted by forward body bias technique to further reduce supply voltage and power dissipation. The post-layout simulation results demonstrate that the proposed 3.4–10.1[Formula: see text]GHz UWB LNA accomplishes a maximum gain of 14.26[Formula: see text]dB with only 2.33[Formula: see text]mW power consumption at 0.8[Formula: see text]V supply voltage, while Noise Figure (NF) is 1.49–3.41[Formula: see text]dB and the chip area is 0.46[Formula: see text]mm2 including test pads (core area is 0.23[Formula: see text]mm2).

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