scholarly journals A Low-Noise, High-Gain, and Small-Size UWB Mixer Utilizing Negative Impedance Technique and Source Input Method

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2655
Author(s):  
Zhaokun Zhou ◽  
Xiaoran Li ◽  
Xinghua Wang ◽  
Wei Gu
Keyword(s):  
Flicker Noise ◽  
Noise Figure ◽  
Supply Voltage ◽  
High Gain ◽  
Low Noise ◽  
Ultra Wideband ◽  
Conversion Gain ◽  
Chip Area ◽  
Input Method ◽  
Impedance Technique

This paper presents an ultra-wideband (UWB) down-conversion mixer with low-noise, high-gain and small-size. The negative impedance technique and source input method are applied for the proposed mixer. The negative impedance achieves the dynamic current injection and increases the mixer output impedance, which reduces the mixer flicker noise and increases its conversion gain. The source input method allows the input matching networks to be cancelled, avoiding the noise and loss introduced by the matching resistors, saving the chip area occupied by the matching inductors. The proposed mixer is designed in 45-nm SOI process provided by GlobalFoundries. The simulation results show a conversion gain of 11.4–14.3 dB, ranging from 3.1 to 10.6 GHz, a minimum noise figure of 9.8 dB, a RF port return loss of less than −11 dB, a port-to-port isolation of better than −48 dB, and a core chip area of 0.16 × 0.16 mm2. The power consumption from a 1 V supply voltage is 2.85 mW.

A Low-Power, High-Gain, and Low-Noise 802.11a Down-Conversion Mixer in 0.35-μm SiGe Bi-CMOS Technology

2017 ◽  
Vol 26 (09) ◽  
pp. 1750134 ◽  
Author(s):  
Jun-Da Chen ◽  
Song-Hao Wang
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Conversion Gain ◽  
Dc Power ◽  
Down Conversion

The paper presents a novel 5.15[Formula: see text]GHz–5.825[Formula: see text]GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-[Formula: see text]m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843[Formula: see text]mm2. The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14[Formula: see text]dB power conversion gain, [Formula: see text]6[Formula: see text]dBm input third-order intercept point (IIP3), 6.85[Formula: see text]dB double side band (DSB) noise figure. The total mixer current is about 1.54[Formula: see text]mA from 1.4[Formula: see text]V supply voltage including output buffer. The total dc power consumption is 2.15[Formula: see text]mW.

scholarly journals A 1.5–40 GHz frequency modulated continuous wave radar receiver front-end

2021 ◽  
pp. 1-11
Author(s):  
Mantas Sakalas ◽  
Niko Joram ◽  
Frank Ellinger
Keyword(s):  
Continuous Wave ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Ultra Wideband ◽  
Front End ◽  
Wave Radar ◽  
Bicmos Technology ◽  
Circuit Components ◽  
High Band

Abstract This study presents an ultra-wideband receiver front-end, designed for a reconfigurable frequency modulated continuous wave radar in a 130 nm SiGe BiCMOS technology. A variety of innovative circuit components and design techniques were employed to achieve the ultra-wide bandwidth, low noise figure (NF), good linearity, and circuit ruggedness to high input power levels. The designed front-end is capable of achieving 1.5–40 GHz bandwidth, 30 dB conversion gain, a double sideband NF of 6–10.7 dB, input return loss better than 7.5 dB and an input referred 1 dB compression point of −23 dBm. The front-end withstands continuous wave power levels of at least 25 and 20 dBm at low band and high band inputs respectively. At 3 V supply voltage, the DC power consumption amounts to 302 mW when the low band is active and 352 mW for the high band case, whereas the total IC size is $3.08\, {\rm nm{^2}}$ .

High Gain and Low Noise Single Balanced Wireless Receiver Front-End Circuit Design

2013 ◽  
Vol 284-287 ◽  
pp. 2647-2651
Author(s):  
Zhe Yang Huang ◽  
Che Cheng Huang ◽  
Jung Mao Lin ◽  
Chung Chih Hung
Keyword(s):  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Total Power ◽  
Cmos Process ◽  
Chip Area ◽  
Wireless Receiver ◽  
Front End ◽  
Total Power Consumption

This paper presents a wideband wireless receiver front-end for 3.1-5.0GHz band group-1 (BG-1) WiMedia application. The front-end circuits are designed in 0.18um standard CMOS process. The experimental results show the maximum conversion power gain is 45.5dB; minimum noise figure is 2.9dB. Input return loss is lower than -9.3dB and output return loss is lower than -6.8dB. The maximum LO conversion power is 0dBm. 3dB working frequency is 1.9GHz (3.1GHz-5.0GHz) Total power consumption is 24.3mW including LNA, mixer and all buffers. Total chip area is 1.27mm2 including dummy and pads.

scholarly journals A Low-Band Multi-Gain LNA Design for Diversity Receive Module with 1.2 dB NF

Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8340
Author(s):  
Behnam S. Rikan ◽  
David Kim ◽  
Kyung-Duk Choi ◽  
Seyed Ali H. Asl ◽  
Joon-Mo Yoo ◽  
...  
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
High Gain ◽  
Low Noise ◽  
Drop Out ◽  
Common Source ◽  
Frequency Bands ◽  
Voltage Compensator ◽  
Current Consumption ◽  
Lna Design

This paper presents and discusses a Low-Band (LB) Low Noise Amplifier (LNA) design for a diversity receive module where the application is for multi-mode cellular handsets. The LB LNA covers the frequency range between 617 MHz to 960 MHz in 5 different frequency bands and a 5 Pole Single Throw (5PST) switch selects the different frequency bands where two of them are for the main and three for the auxiliary bands. The presented structure covers the gain modes from −12 to 18 dB with 6 dB gain steps where each gain mode has a different current consumption. In order to achieve the Noise Figure (NF) specifications in high gain modes, we have adopted a cascode Common-Source (CS) with inductive source degeneration structure for this design. To achieve the S11 parameters and current consumption specifications, the core and cascode transistors for high gain modes (18 dB, 12 dB, and 6 dB) and low gain modes (0 dB, −6 dB, and −12 dB) have been separated. Nevertheless, to keep the area low and keep the phase discontinuity within ±10∘, we have shared the degeneration and load inductors between two cores. To compensate the performance for Process, Voltage, and Temperature (PVT) variations, the structure applies a Low Drop-Out (LDO) regulator and a corner case voltage compensator. The design has been proceeded in a 65-nm RSB process design kit and the supply voltage is 1 V. For 18 dB and −12 dB gain modes as two examples, the NF, current consumption, and Input Third Order Intercept Point (IIP3) values are 1.2 dB and 16 dB, 10.8 mA and 1.2 mA, and −6 dBm and 8 dBm, respectively.

scholarly journals A 77-GHz High Gain Low Noise Receiver for Automatic Radar Applications

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1516
Author(s):  
Shuai Cheng ◽  
Linhong Li ◽  
Niansong Mei ◽  
Zhaofeng Zhang
Keyword(s):  
Flicker Noise ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Receiver Design ◽  
Voltage Controlled Oscillator ◽  
Noise Amplifier ◽  
On Chip ◽  
77 Ghz

In this paper, a high gain 77-GHz receiver with a low noise figure (NF) was designed and implemented in a 40-nm CMOS process. With the purpose of making better use of active devices, an extra inductor, Ld, is adopted in the new neutralization technique. The three-stage differential low noise amplifier (LNA) using the proposed technique improves the voltage gain and reduces the NF. The receiver design utilizes an active double-balanced Gilbert mixer with a transformer coupling network between the transconductance stage and the switch stage. The flicker noise contribution from the switch MOS transistors is largely reduced due to the low DC current of the switch pairs. The LO signal is provided by an on-chip fundamental voltage-controlled oscillator (VCO) with a tuning range from 70.5 to 78.1 GHz. A conversion gain of 32 dB and a NF of 11.86 dB are achieved at 77 GHz by the designed receiver. The LNA as well as the mixer consume a total DC power of 33.2 mW and occupy a core size of 1 × 0.38 mm2.

scholarly journals A concurrent dual-band CMOS low noise amplifier at 2.4/5.2 GHz for WLAN applications

2019 ◽  
Vol 14 (2) ◽  
pp. 555
Author(s):  
S.A.Z. Murad ◽  
A. F. Hasan ◽  
A. Azizan ◽  
A. Harun ◽  
J. Karim
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Notch Filter ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Dual Band ◽  
Common Source ◽  
Noise Amplifier

<span>This paper presents a concurrent dual-band CMOS low noise amplifier (LNA) at operating frequency of 2.4 GHz and 5.2 GHz for WLAN applications. The proposed LNA employed cascode common source to obtain high gain using 0.13-µm CMOS technology. The concurrent dual-band frequencies are matched using LC network band-pass and band-stop notch filter at the input and output stages. The filters help to shape the frequency response of the proposed LNA. The simulation results indicate that the LNA achieves a forward gain of 21.8 dB and 14.22 dB, input return loss of -18 dB and -14 dB at 2.4 GHz and 5.2 GHz, respectively. The noise figure of 4.1 dB and 3.5 dB with the input third-order intercept points 7 dBm and 10 dBm are obtained at 2.4 GHz and 5.2 GHz, respectively. The LNA dissipates 2.4 mW power at 1.2 V supply voltage with a chip size of 1.69 mm2.</span>

scholarly journals Design and implementation of a broad-band high gain low noise amplifier for 3G/4G applications

2021 ◽  
Vol 23 (2) ◽  
pp. 725
Author(s):  
Ahmed M. Abdelmonem ◽  
Ahmed S. I. Amar ◽  
Amir Almslmany ◽  
Ibrahim L. Abdalla ◽  
Fathi A. Farag
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Low Cost ◽  
Broad Band ◽  
High Gain ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Matching Network ◽  
Noise Amplifier

The main aim of the paper is designing and implementing a broadband low-noise-amplifier (LNA) based on compensated matching network techniquein order to get high stable gain, low noise figure, low cost and smaller sizefor 3G/4G communication system applications at 2 GHz with bandwidth 600MHz. The Advanced Design System simulates the proposed circuit (ADS).The implementation was done with a class A bias circuit and a low noise transistor BFU 730F with a lower Noise Figure (NFmin) 0.62 dB. Collectorcurrent is measured to be 5.8mA and base current is 19.1μA with a supply voltage of 2.25V. The new design proposed a (NFmin) of 0.62 dB with a 17.8dB high stable amplifier gain. The microstrip lines (MSL) and compensated matching network techniques were used to improve the LNA’s stability and achieve a good result. The LNA board is implemented and assembled on the FR4 botton layer material. The results are virtually non existence equivalent between the simulated and the measured results.

scholarly journals Design of a LNA in the frequency band 1.8-2.2GHz in 0.13μm CMOS Technology

2005 ◽  
Vol 3 ◽  
pp. 299-303
Author(s):  
E. Di Gioia ◽  
C. Hermann ◽  
H. Klar
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Low Cost ◽  
Operating Mode ◽  
Cmos Technology ◽  
Digital Circuit ◽  
High Gain ◽  
Low Noise ◽  
Noise Amplifier ◽  
Low Supply Voltage

Abstract. The subject of this work is a low noise amplifier (LNA), operating in the frequency range 1.8-2.1GHz. The CMOS 0.13μm technology is used in respect to the low cost of the final device. Among the specifications, a variable gain and an adjustable working frequency are required. In particular, four different working modes are provided: 1.8, 1.9 and 2.1GHz high gain and 2.1GHz low gain. The amplifier is designed to be used as first stage of a receiver for mobile telephony. For this reason low power consumption is taken into consideration (low supply voltage and low drain currents). A simple digital circuit, integrated on-chip, is used to select the operating mode of the LNA by means of two input pins. A Noise figure of 1dB is obtained with a supply voltage of 0.8V.

scholarly journals Ultra-Wide Band LNA Design using Active Inductor with Modified Noise Cancellation Technique

2019 ◽  
Vol 8 (2) ◽  
pp. 2406-2410
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Wide Band ◽  
Low Noise ◽  
Ultra Wide Band ◽  
Active Inductor ◽  
Cmos Process ◽  
Chip Area ◽  
Chip Size ◽  
Lna Design

An Ultra-Wide Band (UWB) Low Noise Amplifier (LNA) is affective in deciding the chip size and in the implementation cost at Radio Frequency applications. The proposed LNA design with an active inductor is a different solution to trounce the habit of passive inductors to cut the chip area. Designed in 90-nm CMOS process, a voltage gain of 9dB to 15.5dB for a supply voltage of 0.9v to 1.8V with a smallest Noise Figure (NF) of 5.7dB is achieved by the LNA, with low power utilization and at 2.40 GHz, with 345um2 of chip area.

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