An Energy-Efficient Switching Scheme for Low-Power SAR ADC Design

2017 ◽  
Vol 27 (01) ◽  
pp. 1850015 ◽  
Author(s):  
Yuhua Liang ◽  
Zhangming Zhu
Keyword(s):  
Low Power ◽  
Successive Approximation ◽  
Energy Efficient ◽  
Figure Of Merit ◽  
Sar Adc ◽  
Analog To Digital Converters ◽  
Cmos Process ◽  
Switching Scheme ◽  
Analog To Digital ◽  
Switching Energy

A novel energy-efficient switching scheme for successive approximation register (SAR) analog-to-digital converters (ADC) is proposed in this paper. The average switching energy of the proposed switching scheme can be reduced by 95.3%, compared with the [Formula: see text]-based scheme. Moreover, the linearity has been also improved significantly. Employing the proposed switching scheme, a 10-bit 100[Formula: see text]kS/s SAR ADC is designed in SMIC 0.18-[Formula: see text]m CMOS process. At a 0.6-V supply, the ADC consumes 43.7[Formula: see text]nW. Consequently, the figure-of-merit (FOM) is optimized to 0.58[Formula: see text]fJ/conversion-step.

Energy-Efficient Switching Scheme with 93.41% Reduction in Capacitor Area for SAR ADC

2019 ◽  
Vol 28 (13) ◽  
pp. 1930010 ◽  
Author(s):  
Shubin Liu ◽  
Haolin Han ◽  
Ruixue Ding
Keyword(s):  
Successive Approximation ◽  
Energy Efficient ◽  
Sar Adc ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Switching Scheme ◽  
Analog To Digital ◽  
Capacitor Array ◽  
Asymmetric Capacitor ◽  
Conventional Scheme

A novel switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the asymmetric capacitor array and splitted MSB capacitor, the proposed scheme achieves 99.09% and 93.41% reductions in the average switching energy and capacitor area, respectively, over the conventional scheme. Moreover, the proposed SAR ADC obtains a moderate linearity performance with max(INL-RMS) less than 0.112 LSB, max(DNL-RMS) less than 0.160 LSB and consumes zero reset energy.

scholarly journals Improved Switching Energy Reduction Approach in Low-Power SAR ADC for Bioelectronics

VLSI Design ◽  
2016 ◽  
Vol 2016 ◽  
pp. 1-6
Author(s):  
Xingyuan Tong ◽  
Tiantian Sun
Keyword(s):  
Low Power ◽  
Sar Adc ◽  
Switching Scheme ◽  
Analog To Digital ◽  
Logic Control ◽  
Switching Energy ◽  
Traditional Structure ◽  
Sinusoidal Input ◽  
Conventional Structure ◽  
Biomedical Electronics

Low-power analog-to-digital converter (ADC) is a crucial part of wearable or implantable bioelectronics. In order to reduce the power of successive-approximation-register (SAR) ADC, an improved energy-efficient capacitor switching scheme of SAR ADC is proposed for implantable bioelectronic applications. With sequence initialization, novel logic control, and capacitive subconversion, 97.6% switching energy is reduced compared to the traditional structure. Moreover, thanks to the top-plate sampling and capacitive subconversion, 87% input-capacitance reduction can be achieved over the conventional structure. A 10-bit SAR ADC with this proposed switching scheme is realized in 65 nm CMOS. With 1.514 KHz differential sinusoidal input signals sampled at 50 KS/s, the ADC achieves an SNDR of 61.4 dB and only consumes power of 450 nW. The area of this SAR ADC IP core is only 136 μm × 176 μm, making it also area-efficient and very suitable for biomedical electronics application.

A Capacitor-Splitting Switching Scheme with Low Total Power Consumption for SAR ADCs

2019 ◽  
Vol 28 (04) ◽  
pp. 1920002 ◽  
Author(s):  
Hao Wang ◽  
Wenming Xie ◽  
Zhixin Chen ◽  
Sijing Cai
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Energy Efficient ◽  
Total Power ◽  
Switching Scheme ◽  
Analog To Digital ◽  
Switching Algorithm ◽  
Good Linearity ◽  
Total Power Consumption

A low-power capacitor-splitting switching algorithm for successive approximation register (SAR) and analog-to-digital converters (ADCs) is proposed. To reduce the total power consumption, it does not require reset energy, which accounts for a large proportion. Besides, energy-efficient one-side double-level switching technique is also utilized from the forth bit cycle. Thus, the proposed switching algorithm requires 26.54 CV[Formula: see text] total switching energy, 16.75% less over the tri-level one. Due to the capacitor-splitting structure, it also shows good linearity performance.

scholarly journals Comparison of 4-Bit SAR ADC Using Different Logic Styles in 90nm Technology

2021 ◽  
pp. 100-108
Author(s):  
Mrs. Lakshmidevi TR ◽  
Mr. K N Jeevan Reddy ◽  
Mr. Ashrith Rao ◽  
Mr. Dhanush Kashyap S ◽  
Ms. Chandini K
Keyword(s):  
Successive Approximation ◽  
Logic Gates ◽  
Design Tool ◽  
Sar Adc ◽  
Analog To Digital Converters ◽  
Battery Life ◽  
Double Pass ◽  
Analog To Digital ◽  
Successive Approximation Register ◽  
Tool Building

In recent years, we have come across a growing need for the design of low power, long battery life Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC). ADCs are the major component of all the systems which need to process an analogue signal obtained from measuring real world parameters and hence they need to be efficient enough depending on the application and power constraint of the device. Speed is also an important parameter as it is used in many real time applications. The basic components of the SAR ADC can be implemented using circuits of various logics available for the logic gates, adders, comparators utilised in it. This paper presents the working of 4-bit successive approximation register analog-to-digital converters (SAR ADC) in three different logics namely, Complementary Metal Oxide Semiconductors (CMOS), Transmission Gates (TG), and Double Pass Transistors (DPL) logics, which were used in the basic components of each major block of the ADC. The aim of this paper here is to compare the various parameters such as area, power consumption and delay between the three different technologies chosen above. The SAR ADCs were implemented for this purpose in 90nm Technology using the Cadence Virtuoso Design Tool building schematics and layouts for the same and calculating the various parameters required for the above-mentioned comparison.

A 0.975 μW 10-bit 100 kS/s SAR ADC with an energy-efficient and area-efficient switching scheme

2017 ◽  
Vol 31 (19-21) ◽  
pp. 1740051 ◽  
Author(s):  
Yunfeng Hu ◽  
Chao Xiong ◽  
Bin Li
Keyword(s):  
Power Supply ◽  
Energy Efficient ◽  
Figure Of Merit ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Digital Converter ◽  
Switching Scheme ◽  
Analog To Digital ◽  
Area Reduction ◽  
Area Efficient

A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an energy-efficient and area-efficient switching scheme was presented. By using C-2C dummy capacitor and an extra reference [Formula: see text] for the last capacitor, the proposed switching scheme achieves 97.65% switching energy saving, 87.2% capacitor area reduction and 47.06% switches reduction, compare to conventional switching scheme. The ADC was implemented in a 180 nm CMOS technology 1.8 V power supply, at sampling rate of 100 kS/s, the ADC achieves an SNDR of 57.84 dB and consumes 0.975 [Formula: see text], resulting in a figure-of-merit (FOM) of 15.3 fJ/conversion-step.

100 MS/s, 10-BIT ADC USING PIPELINED SUCCESSIVE APPROXIMATION

2014 ◽  
Vol 23 (05) ◽  
pp. 1450057
Author(s):  
SAHAR SARAFI ◽  
KHEYROLLAH HADIDI ◽  
EBRAHIM ABBASPOUR ◽  
ABU KHARI BIN AAIN ◽  
JAVAD ABBASZADEH
Keyword(s):  
Successive Approximation ◽  
Sar Adc ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Process Technology ◽  
Total Conversion ◽  
Analog To Digital ◽  
Simulation Results

This paper presents an analog-to-digital converter (ADC), using pipelined successive approximation register (SAR) architecture. The structure which is a combination of SAR-ADC and pipelined ADC benefits from each of their advantages. A new synchronization method is proposed to improve the pipelined SAR-ADC's speed. The proposed method reduces the total conversion without limiting the ADC performance. To evaluate the proposed method a 10-bit 100 MS/s is designed in 0.5 μm CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 9-MHz input with 54.19 dB SNDR while consuming 57.3 mw from a 5-V supply.

Low-Power Capacitor-Splitting DAC with Mixed Switching Schemes for SAR ADCs

2018 ◽  
Vol 27 (10) ◽  
pp. 1850161 ◽  
Author(s):  
Hao Wang ◽  
Lungui Zhong ◽  
Guocheng Zhang
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Switching Scheme ◽  
Successive Approximation Register ◽  
Switching Power ◽  
Switching Energy ◽  
Switching Method ◽  
Analogue To Digital

A low-power capacitor-splitting digital-to-analogue converter (DAC) for successive approximation register (SAR) analogue-to-digital converters (ADCs) is proposed. During the first three bit cycles, with proper switching, there is no average switching power consumption. From the fourth bit cycle, one-side double-level switching scheme or the monotonic one is utilized based on the first two bits. When the first two bits are the same, one-side double-level switching scheme is chosen. Otherwise, the monotonic one is adopted. Thus, the proposed switching method only requires 5.27 CV[Formula: see text] average switching energy, 75.29% less compared to the Sanyal and Sun proposed one.

scholarly journals A Mixed-Signal Programmable Time-Division Power-On-Reset and Volume Control Circuit for High-Resolution Hearing-Aid SoC Application

2018 ◽  
Vol 2018 ◽  
pp. 1-7
Author(s):  
Chengying Chen ◽  
Liming Chen ◽  
Jun Yang
Keyword(s):  
Low Power ◽  
Control Function ◽  
Hearing Aid ◽  
Sar Adc ◽  
Volume Control ◽  
Cmos Process ◽  
Mixed Signal ◽  
Analog To Digital ◽  
Power Application ◽  
Time Division

A mixed-signal programmable Time-Division Power-On-Reset (TD-POR) circuit based on 8-bit Successive Approximation Analog-to-Digital Converter (SAR ADC) for accurate control in low-power hearing-aid System on Chip (SoC) is presented in this paper. The end-of-converter (EOC) signal of SAR ADC is used as the mode-change signal so that the circuit can detect the battery voltage and volume voltage alternately. And the TD-POR circuit also has brown-out reset (BOR) detection capability. Through digital logic circuit, the POR, BOR threshold, and delay time can be adjusted according to the system requirement. The circuit is implemented in SMIC 0.13 μm 1P8M CMOS process. The measurement results show that, in 1 V power supply, the POR, BOR, and volume control function are accomplished. The detection resolution is the best among previous work. With 120 Hz input signal and 15 kHz clock, the ADC shows that Signal to Noise plus Distortion Ratio (SNDR) is 46.5 dB and Effective Number Of Bits (ENOB) is 7.43 bits. Total circuit power consumption is only 86 μw for low-power application.

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