Phase locked loop-based clock synthesizer for reconfigurable analog-to-digital converters

This paper presents the complete design of a phase locked loop-based clock synthesizer for reconfigurable analog-to-digital converters. The synthesizer was implemented in TSMC 65 nm CMOS process technology and the presented results were obtained from extracted layout view with parasitics. The synthesizer generates clock frequencies ranging from 40 to 230 MHz considering a reference frequency of 10 MHz and a supply voltage of 1.2 V. Worst case current consumption is 634 $$\mu $$ μ W, settling time is 6 $$\mu $$ μ s, maximum jitter is 1.3 ns in a 0.037 mm$$^2$$ 2 area. Performance was validated in a test $$\Sigma \Delta $$ Σ Δ Modulator with bandwidths of 200 kHz, 500 kHz and 2 MHz, and oversampling frequencies of 40, 60 and 80 MHz respectively, with negligible signal-to-noise ratio degradation compared to an ideal clock.

Comparison of 4-Bit SAR ADC Using Different Logic Styles in 90nm Technology

In recent years, we have come across a growing need for the design of low power, long battery life Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC). ADCs are the major component of all the systems which need to process an analogue signal obtained from measuring real world parameters and hence they need to be efficient enough depending on the application and power constraint of the device. Speed is also an important parameter as it is used in many real time applications. The basic components of the SAR ADC can be implemented using circuits of various logics available for the logic gates, adders, comparators utilised in it. This paper presents the working of 4-bit successive approximation register analog-to-digital converters (SAR ADC) in three different logics namely, Complementary Metal Oxide Semiconductors (CMOS), Transmission Gates (TG), and Double Pass Transistors (DPL) logics, which were used in the basic components of each major block of the ADC. The aim of this paper here is to compare the various parameters such as area, power consumption and delay between the three different technologies chosen above. The SAR ADCs were implemented for this purpose in 90nm Technology using the Cadence Virtuoso Design Tool building schematics and layouts for the same and calculating the various parameters required for the above-mentioned comparison.