Clock gating for power optimization in ASIC design cycle theory & practice

2008 ◽  
Author(s):  
Jairam S ◽  
Madhusudan Rao ◽  
Jithendra Srinivas ◽  
Parimala Vishwanath ◽  
Udayakumar H ◽  
...  
Keyword(s):  
Power Optimization ◽  
Clock Gating ◽  
Asic Design ◽  
Design Cycle

scholarly journals Low Power Design for ASIC Cores

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 317-331
Author(s):  
Alvar Dean ◽  
David Garrett ◽  
Mircea R. Stan ◽  
Sebastian Ventrone
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Low Power Design ◽  
Clock Gating ◽  
Asic Design ◽  
Design Techniques

A semicustom ASIC design methodology is used to develop a low power DSP core for mobile (battery powered) applications. Different low power design techniques are used, including dual voltage, low power library elements, accurate power reporting, pseudomicrocode, transition-once logic, clock gating, and others.

Clock Gating Efficiency and Impact on Power Optimization During Synthesis Flow

2021 ◽  
Author(s):  
Yassine Attaoui ◽  
Mohamed Chentouf ◽  
Zine El Abidine Alaoui Ismaili ◽  
Aimad El Mourabit
Keyword(s):  
Power Optimization ◽  
Clock Gating
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