Crown Defect Reduction and Cp Yield Improvement for High Voltage Power Management IC Product

2019 ◽  
Vol 27 (1) ◽  
pp. 377-382
Author(s):  
Guan-Qun Zhang ◽  
Athics Gu ◽  
Yi-Hui Lin ◽  
Peng Sun ◽  
Jiwei Zhang ◽  
...  
Keyword(s):  
Power Management ◽  
High Voltage ◽  
Yield Improvement ◽  
Defect Reduction ◽  
Power Management Ic

Improve the Mechanisms Product Yield through Cycle Time Optimization

2013 ◽  
Vol 433-435 ◽  
pp. 2409-2412
Author(s):  
Fei Xiong ◽  
Jin Yao
Keyword(s):  
Cycle Time ◽  
Product Yield ◽  
Driving Cycle ◽  
Manufacturing Environment ◽  
Yield Improvement ◽  
Defect Reduction ◽  
Management Level ◽  
Time Optimization ◽  
Quality Product ◽  
Made In

In mechanisms manufacturing environment, factory management level is always trying to achieve higher product yield to ship more quality product to the customers. In this paper, we will show the yield improvement based on cycle time reduces. Yield organization has established excellent systems for driving defect reduction. Established a clear set of core principles that would help drive a new way of driving cycle time improvement. Discuss the key findings captured through yield benchmarking activities. There are three core principles outlined above and the associated changes made in manufacturing to embrace these principles.

Study on Defect Reduction and Yield Improvement of MIM Al Deposition Process

2019 ◽  
Vol 44 (1) ◽  
pp. 791-796
Author(s):  
Vincent Chang ◽  
Athics Gu ◽  
Terry Li ◽  
Ji-Wei Zhang ◽  
Jian-Yong Jiang ◽  
...  
Keyword(s):  
Deposition Process ◽  
Yield Improvement ◽  
Defect Reduction

A New Power Management IC Architecture for Envelope Tracking Power Amplifier

2011 ◽  
Vol 59 (7) ◽  
pp. 1796-1802 ◽  
Author(s):  
Jinsung Choi ◽  
Dongsu Kim ◽  
Daehyun Kang ◽  
Bumman Kim
Keyword(s):  
Power Management ◽  
Power Amplifier ◽  
Envelope Tracking ◽  
Power Management Ic

Reliability LU Appropriate Designs in an HV nLDMOS

2012 ◽  
Vol 271-272 ◽  
pp. 1082-1086
Author(s):  
Shen Li Chen ◽  
Tzung Shian Wu
Keyword(s):  
Power Management ◽  
High Voltage ◽  
Drain Side ◽  
Novel Method

In an nLDMOS, both the drain-side and source-side engineering by adding Nad and Pad layers to obtain a weak snapback characteristic are presented in this work. In this paper, we will detailedly discuss the trigger voltage (Vt1) and holding voltage (Vh) distribution of a novel high-voltage (HV) nLDMOS device. It’s a novel method to reduce the Vt1 and to increase the Vh. Therefore, these efforts will be very suitable for the HV applications in power management ICs.

scholarly journals High-voltage circuits for power management on 65 nm CMOS

2015 ◽  
Vol 13 ◽  
pp. 109-120
Author(s):  
S. Pashmineh ◽  
D. Killat
Keyword(s):  
Power Management ◽  
Circuit Design ◽  
High Voltage ◽  
Cmos Technology ◽  
Buck Converter ◽  
Drop Out ◽  
Voltage Regulator ◽  
Error Amplifier ◽  
Load Regulation ◽  
Switching Characteristics

Abstract. This paper presents two high-voltage circuits used in power management, a switching driver for buck converter with optimized on-resistance and a low dropout (LDO) voltage regulator with 2-stacked pMOS pass devices. The circuit design is based on stacked MOSFETs, thus the circuits are technology independent. High-voltage drivers with stacked devices suffer from slow switching characteristics. In this paper, a new concept to adjust gate voltages of stacked transistors is introduced for reduction of on-resistance. According to the theory, a circuit is proposed that drives 2 stacked transistors of a driver. Simulation results show a reduction of the on-resistance between 27 and 86 % and a reduction of rise and fall times between 16 and 83 % with a load capacitance of 150 pF at various supply voltages, compared to previous work. The concept can be applied to each high-voltage driver that is based on a number (N) of stacked transistors. The high voltage compatibility of the low drop-out voltage regulator (LDO) is established by a 2-stacked pMOS transistors as pass device controlled by two regulators: an error amplifier and a 2nd amplifier adjusting the division of the voltages between the two pass transistors. A high GBW and good DC accuracy in line and load regulation is achieved by using 3-stage error amplifiers. To improve stability, two feedback loops are utilized. In this paper, the 2.5 V I/O transistors of the TSMC 65 nm CMOS technology are used for the circuit design.

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