scholarly journals Integrated VCOs for Medical Implant Transceivers

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-10 ◽  
Author(s):  
Ahmet Tekin ◽  
Mehmet R. Yuce ◽  
Wentai Liu
Keyword(s):  
Data Transfer ◽  
Supply Voltage ◽  
Low Frequency ◽  
Federal Communication Commission ◽  
Implantable Devices ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Medical Implant ◽  
Shift Keying ◽  
Lc Tank

The 402–405 MHz medical implant communication service (MICS) band has recently been allocated by the US Federal Communication Commission (FCC) with the potential to replace the low-frequency inductive coupling techniques in implantable devices. This band was particularly chosen to provide full-integration, low-power, faster data transfer, and longer communication range. This paper investigates the design of a voltage-controlled oscillator (VCO) that will be an essential building block of such wireless implantable devices operating in the MICS service band. Three different integrated quadrature VCOs that meet the requirements of the MICS standard are designed in 0.18 μm TSMC CMOS process to propose an optimum choice. Their performances in terms of power consumption, die area, linearity, and phase noise are compared. The fabricated VCOs are a four-stage differential ring VCO, an LC tank VCO directly loaded with a poly-phase filter, and an 800 MHz LC tank VCO with a high-frequency master-slave divider. All three architectures target a VCO gain of Kvco = 15 MHz/V with 3 calibration control and 2 frequency-shift keying (FSK) control signals and are designed for 1.5 V supply voltage in a 0.18-μm standard CMOS process.

Design and analysis of a low noise CMOS charge pump phase locked loop circuit

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Power Supply Voltage ◽  
Supply Noise

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

Ground-Adjustable Inductor for Wide-Tuning VCO Design

2012 ◽  
Vol 256-259 ◽  
pp. 2373-2378
Author(s):  
Wu Shiung Feng ◽  
Chin I Yeh ◽  
Ho Hsin Li ◽  
Cheng Ming Tsao
Keyword(s):  
Power Consumption ◽  
Tuning Range ◽  
Supply Voltage ◽  
Wide Band ◽  
Ultra Wide Band ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Wide Tuning Range ◽  
Chip Area ◽  
Ground Plate

A wide-tuning range voltage-controlled oscillator (VCO) with adjustable ground-plate inductor for ultra-wide band (UWB) application is presented in this paper. The VCO was implemented by standard 90nm CMOS process at 1.2V supply voltage and power consumption of 6mW. The tuning range from 13.3 GHz to 15.6 GHz with phase noise between -99.98 and -115dBc/Hz@1MHz is obtained. The output power is around -8.7 to -9.6dBm and chip area of 0.77x0.62mm2.

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

2019 ◽  
Vol 29 (08) ◽  
pp. 2050130 ◽  
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Dead Zone ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Control Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Cmos Inverter ◽  
Digital Cmos

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

Design Methodology of Ultra-Low-Power LC-VCOs for IoT Applications

2019 ◽  
Vol 28 (07) ◽  
pp. 1950122 ◽  
Author(s):  
Imen Ghorbel ◽  
Fayrouz Haddad ◽  
Wenceslas Rahajandraibe ◽  
Mourad Loulou
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Ultra Low Power ◽  
Trade Offs ◽  
Process Measurements ◽  
Lc Vco

A design methodology of CMOS LC voltage-controlled oscillator (VCO) is proposed in this paper. The relation between components and specifications of the LC-VCO is studied to easily identify its design trade-offs. This methodology has been applied to design ultra-low-power LC-VCOs for different frequency bands. An LC-VCO based on the current reuse technique has been realized with the proposed methodology in 0.13[Formula: see text][Formula: see text]m CMOS process. Measurements present an ultra-low power consumption of only 262[Formula: see text][Formula: see text]W drawn from 1[Formula: see text]V supply voltage. The measured frequency tuning range is about 10% between 2.179[Formula: see text]GHz and 2.409[Formula: see text]GHz. The post-layout simulation presents a phase noise (PN) of [Formula: see text][Formula: see text]dBc/Hz, while the measured PN is [Formula: see text][Formula: see text]dBc/Hz.

Low Phase Noise and Low Power Voltage-Controlled-Oscillator Using Current-Reuse Techniques for Wireless Communication Circuits

2013 ◽  
Vol 479-480 ◽  
pp. 1010-1013
Author(s):  
Tsung Han Han ◽  
Meng Ting Hsu ◽  
Cheng Chuan Chung
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Supply Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Chip Area ◽  
Voltage Controlled Oscillators ◽  
Communication Circuits ◽  
5 Ghz ◽  
Low Phase Noise

In this paper, we present low phase noise and low power of the voltage-controlled oscillators (VCOs) for 5 GHz applications. This chip is implemented by Taiwan Semiconductor Manufacturing Company (TSMC) standard 0.18 μm CMOS process. The designed circuit topology is included a current-reused configuration. It is adopted memory-reduced tail transistor technique. At the supply voltage 1.5 v, the measured output phase noise is-116.071 dBc/Hz at 1MHz offset frequency from the carrier frequency 5.2 GHz. The core power consumption is 3.7 mW, and tuning range of frequency is about 1.3 GHz from 4.8 to 6.1 GHz. The chip area is 826.19 × 647.83 um2.

scholarly journals A Millimeter-Wave CMOS Injection-Locked BPSK Transmitter in 65-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 598 ◽  
Author(s):  
Jiafu Lin ◽  
He Peng ◽  
Qichao Yang ◽  
Roc Berenguer ◽  
Gui Liu
Keyword(s):  
Millimeter Wave ◽  
High Speed ◽  
Data Transfer ◽  
Cmos Process ◽  
Chip Area ◽  
Shift Keying ◽  
High Speed Data ◽  
Minimum Delay ◽  
Increasing Demand ◽  
Binary Phase Shift Keying

In order to provide gigabit per second wireless communication, various standards have been proposed and implemented in recent years. Since the millimeter-wave (mm-wave) communication enables uncompressed high-speed data transfer with a minimum delay, it is considered to be the most promising technology to alleviate the pressure of the increasing demand of the spectrum resource. In this paper, a compact and highly efficient mm-wave transmitter is presented. The proposed injection-locked binary phase-shift keying (BPSK) transmitter can deliver a 10.2 dBm output with an efficiency over 10%. The proposed transmitter occupies 0.105 mm2 chip area in 65 nm CMOS process.

A Wide Locking Range and Low Power Divide-by-2/3 LC Injection-Locked Frequency Divider

2015 ◽  
Vol 25 (02) ◽  
pp. 1650013 ◽  
Author(s):  
Wanhang Gao ◽  
Wei Zhang ◽  
Yanyan Liu
Keyword(s):  
Supply Voltage ◽  
Frequency Divider ◽  
Cmos Process ◽  
Incident Power ◽  
Nmos Transistor ◽  
The Core ◽  
Locking Range ◽  
In Series ◽  
Wide Locking Range ◽  
Lc Tank

A direct divide-by-2/3 LC injection-locked frequency divider (ILFD) is presented in this paper. The proposed ILFD circuit is based on a CMOS LC tank oscillator coupled with an injection NMOS transistor in series with an inductor. Together with body-biased technique and current-reused topology, the locking range of the ILFD is improved and the power consumption is reduced. The circuit is implemented in a 0.18[Formula: see text][Formula: see text]m standard RF CMOS process. At the incident power of 0[Formula: see text]dBm, the measured locking range of the divide-by-2 and divide-by-3 modes are from 5.37[Formula: see text]GHz to 7.68 (8.07[Formula: see text]GHz to 11.4[Formula: see text]GHz) GHz, and the core circuit without buffers consumes 3[Formula: see text]mW at the supply voltage of 1.5[Formula: see text]V. The chip only occupies [Formula: see text] without the pads and the buffers.

scholarly journals A 0.8 V, 5.3–5.9 GHz Sub-Sampling PLL with 196.5 fsrms Integrated Jitter and −251.6 dB FoM

Sensors ◽  
2021 ◽  
Vol 21 (22) ◽  
pp. 7648
Author(s):  
Shi Zuo ◽  
Jianzhong Zhao ◽  
Yumei Zhou
Keyword(s):  
Phase Noise ◽  
Root Mean Square ◽  
Supply Voltage ◽  
Cmos Process ◽  
Type I ◽  
Voltage Controlled Oscillator ◽  
Mean Square ◽  
Frequency Range ◽  
Output Frequency ◽  
Zero Phase

This paper proposes a hybrid dual path sub-sampling phase-locked loop (SSPLL), including a proportional path (P-path) and an integral path (I-path), with 0.8 V supply voltage. A differential master–slave sampling filter (MSSF), replacing the sub-sampling charge pump (SSCP), composed the P-path to avoid the degraded feature caused by the decreasing of the supply voltage. The I-path is built by a rail-to-rail SSCP to suppress the phase noise of the voltage-controlled oscillator (VCO) and avoid the trouble of locking at the non-zero phase offset (as in type-I PLL). The proposed design is implemented in a 40-nm CMOS process. The measured output frequency range is from 5.3 to 5.9 GHz with 196.5 fs root mean square (RMS) integrated jitter and −251.6 dB FoM.

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