scholarly journals A Swarm Random Walk Based Method for the Standard Cell Placement Problem

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Najwa Altwaijry ◽  
Mohamed El Bachir Menai
Keyword(s):  
Simulated Annealing ◽  
Random Walk ◽  
Hybrid Methods ◽  
Vlsi Design ◽  
Standard Cell ◽  
Placement Problem ◽  
Benchmark Suite ◽  
Cell Placement ◽  
On Chip ◽  
Min Cut

The standard cell placement (SCP) problem is a well-studied placement problem, as it is an important step in the VLSI design process. In SCP, cells are placed on chip to optimize some objectives, such as wirelength or area. The SCP problem is solved using mainly four basic methods: simulated annealing, quadratic placement, min-cut placement, and force-directed placement. These methods are adequate for small chip sizes. Nowadays, chip sizes are very large, and hence, hybrid methods are employed to solve the SCP problem instead of the original methods by themselves. This paper presents a new hybrid method for the SCP problem using a swarm intelligence-based (SI) method, called SwarmRW (swarm random walk), on top of a min-cut based partitioner. The resulting placer, called sPL (swarm placer), was tested on the PEKU benchmark suite and compared with several related placers. The obtained results demonstrate the effectiveness of the proposed approach and show that sPL can achieve competitive performance.

scholarly journals A Fast Clustering-Based Min-Cut Placement Algorithm With Simulated-Annealing Performance

VLSI Design ◽  
1996 ◽  
Vol 5 (1) ◽  
pp. 37-48 ◽  
Author(s):  
Youssef Saab
Keyword(s):  
Simulated Annealing ◽  
Integrated Circuits ◽  
Large Scale ◽  
Optimization Problem ◽  
Wire Length ◽  
Constrained Optimization Problem ◽  
Placement Problem ◽  
Constructive Methods ◽  
Placement Algorithm ◽  
Min Cut

Placement is an important constrained optimization problem in the design of very large scale (VLSI) integrated circuits [1–4]. Simulated annealing [5] and min-cut placement [6] are two of the most successful approaches to the placement problem. Min-cut methods yield less congested and more routable placements at the expense of more wire-length, while simulated annealing methods tend to optimize more the total wire-length with little emphasis on the minimization of congestion. It is also well known that min-cut algorithms are substantially faster than simulated-annealing-based methods. In this paper, a fast min-cut algorithm (ROW-PLACE) for row-based placement is presented and is empirically shown to achieve simulated-annealing-quality wire-length on a number of benchmark circuits. In comparison with Timberwolf 6 [7], ROW-PLACE is at least 12 times faster in its normal mode and is at least 25 times faster in its faster mode. The good results of ROW-PLACE are achieved using a very effective clustering-based partitioning algorithm in combination with constructive methods that reduce the wire-length of nets involved in terminal propagation.

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