Torque Comparison Between Two Passive Self-Ligating Brackets with Respect to Interbracket Wire Dimensions and Types: A Finite Element Analysis

Objective: This study aimed to analyze the expression of torque between 2 passive self-ligating brackets by simulating different clinical situations using finite element analysis. Material and Methods: Two passive self-ligating brackets, that is, Damon Q (Ormco, Glendora, California) and Smart Clip (3M Unitek, Monrovia, California), were 3D modeled using micro-computed tomography. ANSYS V14.5 software was used for analysis. Archwire and bracket interactions were simulated to measure torque expression by changing wire alloys (stainless steel [SS] and titanium molybdenum [TMA]) and interbracket dimensions. Results: Damon Q brackets generated higher torque values compared to Smart Clip brackets with both SS and TMA wires. Damon Q brackets generated the highest torquing moment of 25.72 Nmm and 7.45 Nmm, while Smart Clip brackets generated 22.25 Nmm and 7.31 Nmm with 0.019 × 0.025″ SS and TMA wires, respectively, at an interbracket distance of 12 mm. Torquing moments decreased for Damon Q and Smart Clip brackets when wire length increased from 12 mm to 16 mm. Conclusion: Damon Q with 0.019 × 0.025″wires exhibited superior torquing characteristics as compared to Smart Clip brackets with similar archwires.

Wire length optimization of VLSI circuits using IWO algorithm and its hybrid

Purpose Advancement in optimization of VLSI circuits involves reduction in chip size from micrometer to nanometer level as well as fabrication of a billions of transistors in a single die where global routing problem remains significant with a trade-off of power dissipation and interconnect delay. This paper aims to solve the increased complexity in VLSI chip by minimization of the wire length in VLSI circuits using a new approach based on nature-inspired meta-heuristic, invasive weed optimization (IWO). Further, this paper aims to achieve maximum circuit optimization using IWO hybridized with particle swarm optimization (PSO). Design/methodology/approach This paper projects the complexities of global routing process of VLSI circuit design in mapping it with a well-known NP-complete problem, the minimum rectilinear Steiner tree (MRST) problem. IWO meta-heuristic algorithm is proposed to meet the MRST problem more efficiently and thereby reducing the overall wire-length of interconnected nodes. Further, the proposed approach is hybridized with PSO, and a comparative analysis is performed with geosteiner 5.0.1 and existing PSO technique over minimization, consistency and convergence against available benchmark. Findings This paper provides high performance–enhanced IWO algorithm, which keeps in generating low MRST value, thereby successful wire length reduction of VLSI circuits is significantly achieved as evident from the experimental results as compared to PSO algorithm and also generates value nearer to geosteiner 5.0.1 benchmark. Even with big VLSI instances, hybrid IWO with PSO establishes its robustness over achieving improved optimization of overall wire length of VLSI circuits. Practical implications This paper includes implications in the areas of optimization of VLSI circuit design specifically in the arena of VLSI routing and the recent developments in routing optimization using meta-heuristic algorithms. Originality/value This paper fulfills an identified need to study optimization of VLSI circuits where minimization of overall interconnected wire length in global routing plays a significant role. Use of nature-based meta-heuristics in solving the global routing problem is projected to be an alternative approach other than conventional method.

Multivariate Quadratic Nonlinear Regression Model of the Ultimate Pull-Out Load of Electrohydraulic Expansion Joints Based on Response Surface Methodology

Electrohydraulic expansion joining has great potential for joining the light weight and high strength thin-walled pipes due to its high strain rate. Based on the central composite design (CCD) of response surface methodology, multiple experiments of electrohydraulic expansion joining process were performed. The multivariate quadratic nonlinear regression model between process parameters (discharge voltage, wire length, and wire diameter) and the ultimate pull-out load of the joints was established. The results revealed that discharge voltage, wire length and wire diameter all had a significant effect on the ultimate pull-out load. The discharge voltage had the most significant effect. The interaction between the discharge voltage and the wire diameter had a significant effect on the ultimate pull-out load. The optimal parameter combination (discharge voltage = 6 kV, wire length = 10 mm, wire diameter = 0.833 mm) was obtained and verified through the experiments. This study would provide guidance for the choice of the process parameters in real applications.

WEDM single crater asymmetry

In wire electrical discharge machining (WEDM), the erosion is made through a series of overlapped craters. The shape of these craters has a relevant impact on the characteristics of the machined surface, from surface roughness to heat effects during the spark. Current models on EDM process do not represent specific WEDM characteristics, such as radial asymmetry of the crater or geometrical effects on the crater shape. In order to characterize the crater’s dimensions in WEDM, single discharge experiments are performed on polished steel for pulses with different energy levels. A 3D optical microscope is used to map the single craters’ topographies (experimental work). To capture the craters’ dimensions, an ellipsoidal equation is applied with a Levenberg–Marquardt algorithm. The ellipsoidal equation is capable of identifying the dimensions along the wire length, perpendicular to the wire and the depth of the crater. The ratio between the dimension along the wire and the dimension perpendicular to the wire is used to define a crater’s aspect ratio and characterizes its elongation. The aspect ratio of the single craters is found to be dependent on the pulse energy. Low-energy pulses create rounder craters, while high-energy pulses form elongated craters that are longer along the wire length. Such behavior suggests that the crater formation is constricted by the wire geometry, having a preferential direction of growth, along the wire length.

X-architecture Steiner minimal tree algorithm based on multi-strategy optimization discrete differential evolution

Global routing is an important link in very large scale integration (VLSI) design. As the best model of global routing, X-architecture Steiner minimal tree (XSMT) has a good performance in wire length optimization. XSMT belongs to non-Manhattan structural model, and its construction process cannot be completed in polynomial time, so the generation of XSMT is an NP hard problem. In this paper, an X-architecture Steiner minimal tree algorithm based on multi-strategy optimization discrete differential evolution (XSMT-MoDDE) is proposed. Firstly, an effective encoding strategy, a fitness function of XSMT, and an initialization strategy of population are proposed to record the structure of XSMT, evaluate the cost of XSMT and obtain better initial particles, respectively. Secondly, elite selection and cloning strategy, multiple mutation strategies, and adaptive learning factor strategy are presented to improve the search process of discrete differential evolution algorithm. Thirdly, an effective refining strategy is proposed to further improve the quality of the final Steiner tree. Finally, the results of the comparative experiments prove that XSMT-MoDDE can get the shortest wire length so far, and achieve a better optimization degree in the larger-scale problem.

IC Floorplanning Optimization using Simulated Annealing with Order-based Representation

Integrated Circuits (IC) floorplanning is an important step in the integrated circuit physical design; it influences the area, wire-length, delay etc of an IC. In this paper, Order Based (OB) representation has been proposed for fixed outline floorplan with Simulated Annealing (SA) algorithm. To optimize the IC floorplan, two physical quantities have been considered such as area, and wire-length for hard IP modules. Optimization of the IC floorplan works in two phases. In the first phase, floorplans are constructed by proposed representation without any overlapping among the modules. In the second phase, Simulated Annealing algorithm explores the packing of all modules in floorplan to find better optimal performances i.e. area and wire-length. The Experimental results on Microelectronic Center of North Carolina benchmark circuits show that our proposed representation with SA algorithm performs better for area and wire-length optimization than the other methods. The results are compared with the solutions derived from other algorithms. The significance of this research work is improvement in optimized area and wire-length for modern IC.

KINERJA SERAT KAWAT BENDRAT SEBAGAI BAHAN TAMBAH BETON FAS 0.4

Concrete is the most important part of a construction building. The purpose of this study was to examine how the comparison of physical and mechanical properties and optimum levels of the addition of straight tie wire as an added material with a water-cement ratio of 0.4. The percentage of addition of straight tie wire: 0%, 0.5%, 0.75%, 1.0%, of the total weight of the specimen with a tie-wire length of 8 cm. The test specimens for compressive strength, modulus of elasticity, and split tensile are in the form of a cylinder with a diameter of 15 cm and a height of 30 cm, and the specimen for flexural strength is a block with a length of 50 cm, a width of 10 cm and a height of 10 cm. The results show that the maximum compressive strength test on tie wire occurred at a percentage of 0.75% of 16.56 MPa. The maximum modulus of elasticity in tie wire occurred at a percentage of 0.75% of 15184.56 MPa. The maximum split tensile strength of tie wire occurred in a percentage of 0.75% of 1.165 MPa, and the maximum flexural strength of tie wire occurs at a percentage of 0.75% of 1.950 MPa. The research results concluded that the addition of a straight tie-wire to the concrete mixture could increase the compressive strength, split tensile strength, tensile strength, and elastic modulus of concrete.

A System-Level Exploration of Binary Neural Network Accelerators with Monolithic 3D Based Compute-in-Memory SRAM

Binary neural networks (BNNs) are adequate for energy-constrained embedded systems thanks to binarized parameters. Several researchers have proposed the compute-in-memory (CiM) SRAMs for XNOR-and-accumulation computations (XACs) in BNNs by adding additional transistors to the conventional 6T SRAM, which reduce the latency and energy of the data movements. However, due to the additional transistors, the CiM SRAMs suffer from larger area and longer wires than the conventional 6T SRAMs. Meanwhile, monolithic 3D (M3D) integration enables fine-grained 3D integration, reducing the 2D wire length in small functional units. In this paper, we propose a BNN accelerator (BNN_Accel), composed of a 9T CiM SRAM (CiM_SRAM), input buffer, and global periphery logic, to execute the computations in the binarized convolution layers of BNNs. We also propose CiM_SRAM with the subarray-level M3D integration (as well as the transistor-level M3D integration), which reduces the wire latency and energy compared to the 2D planar CiM_SRAM. Across the binarized convolution layers, our simulation results show that BNN_Accel with the 4-layer CiM_SRAM reduces the average execution time and energy by 39.9% and 23.2%, respectively, compared to BNN_Accel with the 2D planar CiM_SRAM.

Wire-Length and Run-Time Optimization in FPGA Placement Using Hybrid Iterative Algorithms

This paper introduces hybrid iterative algorithms that combine Particle Swarm Optimization (PSO) and Simulated Annealing (SA) algorithms for Field Programmable Gate Array (FPGA) placement by considering adaptive inertia weight and local minima avoidance. The algorithms target to optimize the wire-length of the nets, run time and critical path delay in the placement of logic blocks. Using the adaptive inertia weight parameter and local minima avoidance, the hybrid PSO-SA algorithm is modified to Time-varying PSO-SA (TPSO-SA) and Modified PSO-SA (MPSO-SA) algorithm, respectively. These different hybrid PSO-SA algorithms are checked for efficiency by comparing with the Versatile Place and Route (VPR) algorithm of the Verilog to Routing (VTR) tool using Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The hybrid PSO-SA algorithms give 5–37% better results for wire-length cost and 20–58% reduction in runtime compared to the VPR placement algorithm on different benchmark circuits. Critical path delay is also taken into consideration.