scholarly journals System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation

2019 ◽  
Vol 15 (1) ◽  
pp. 1-10
Author(s):  
Sohaib Majzoub ◽  
Mottaqiallah Taouil ◽  
Said Hamdioui
Keyword(s):  
Threshold Voltage ◽  
Process Variation ◽  
Voltage Scaling ◽  
System Level ◽  
20 Nm

scholarly journals Channel Length Biasing for Improving Read Margin of the 8T SRAM at Near Threshold Operation

Electronics ◽  
2019 ◽  
Vol 8 (6) ◽  
pp. 611 ◽  
Author(s):  
Ik Joon Chang ◽  
Yesung Kang ◽  
Youngmin Kim
Keyword(s):  
Threshold Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Channel Length ◽  
Voltage Level ◽  
Exact Data ◽  
Optimum Energy ◽  
The Stability ◽  
20 Nm ◽  
Near Threshold

Reducing a supply voltage in order to minimize power consumption in memory is a major design consideration in this field of study. In static random access memory (SRAM), optimum energy can be achieved by reducing the voltage near the threshold voltage level for near threshold voltage computing (NTC). However, lowering the operational voltage drastically degrades the stability of SRAM. Thus, in conventional 6T SRAM, it is almost impossible to read exact data, even when a small process variation occurs. To address this problem, an 8T SRAM structure is proposed which can be widely used for improving the read stability at lower voltage operation. In this paper, we investigate the channel length biasing effect on the read access transistor of the 8T SRAM in NTC and compare this with 6T SRAM. Read stability can be improved by suppressing the leakage current due to the longer channel length. Simulation results show that, in NTC, up to a 12× read-error reduction can be achieved by the 20 nm channel length biasing in the 8T SRAM compared to 6T SRAM.

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