scholarly journals Pseudorandom Testing – A Study of the Effect of the Generator Type

10.14311/686 ◽  
2005 ◽  
Vol 45 (2) ◽  
Author(s):  
P. Fišer ◽  
H. Kubátová
Keyword(s):  
Test Pattern ◽  
Pattern Generator ◽  
Fault Coverage ◽  
Linear Feedback ◽  
Random Pattern ◽  
Generating Polynomial ◽  
Primitive Polynomials ◽  
Generator Type ◽  
Pattern Generators ◽  
Test Vectors

The test pattern generator produces test vectors that are applied to the tested circuit during pseudo-random testing of combinational circuits. The nature of the generator thus directly influences the fault coverage achieved. In this paper we discuss the influence of the type of pseudo-random pattern generator on stuck-at fault coverage. Linear feedback shift registers (LFSRs) are mostly used as test pattern generators, and the generating polynomial is primitive to ensure the maximum period. We have shown that it is not necessary to use primitive polynomials, and moreover that their using is even undesirable in most cases. This fact is documented by statistical graphs. The necessity of the proper choice of a generating polynomial and an LFSR seed is shown here, by designing a mixed-mode BIST for the ISCAS benchmarks.An alternative to LFSRs are cellular automata (CA). We study the effectiveness of CA when used as pseudo-random pattern generators. The observations are documented by statistical results. 

scholarly journals VLSI Implementation of Linear Feedback Shift Register (LFSR) based Test Pattern Generator for Pseudo Exhaustive Testing

2020 ◽  
Vol 9 (7) ◽  
pp. 812-820
Keyword(s):  
High Speed ◽  
Test Pattern ◽  
Modular Design ◽  
Binary Sequence ◽  
Pattern Generator ◽  
Fault Coverage ◽  
Digital Systems ◽  
Linear Feedback ◽  
Design Work ◽  
Test Volume

Advanced strides of improvement in programmable logic density, enhancements in speed and hardware description language (HDL) are empowering design engineers to implement highly performing and testable digital systems. Linear feedback shift registers (LFSR) are the critical elements in the testing and self testing of contemporary complex electronic systems like processors, Built-in-self-test (BIST) controllers and integrated circuits (ICs) etc. Fundamentally BIST is a Design-forTestability (DFT) technique meant to configure testing functions physically with the circuit under test (CUT). To enhance the percentage of fault coverage as a part of BIST operations (testing the IC), LFSRs are deployed (as test pattern generator) to generate the test vectors inside logic BIST for testing digital systems. Proposed work is focused upon designing a fast adder based variable length pseudorandom binary sequence pattern generator (PRBSPG) and experimental validations. LFSR possess characteristics of high speed, better encoding efficiency, high fault coverage, low test volume data and low power consumption specially suitable in processing environment where uniform distribution random numbers are required. Verilog HDL is employed for structuring the modular design units while Xilinx ISE tool is deployed for validating the proposed LFSR design work and associated modular units.a

scholarly journals Implementation and Utilization of LBIST for 16 bit ALU

2019 ◽  
Vol 8 (10) ◽  
pp. 1915-1920
Keyword(s):  
Low Power ◽  
Test Pattern ◽  
Pattern Generator ◽  
Binary Sequences ◽  
Linear Feedback ◽  
Random Pattern ◽  
Power Test ◽  
Low Power Test ◽  
Power Pattern ◽  
Selection Of

This paper refers to implementation of Low Power Built-In-Self-Test (LBIST) and its utilization for testing of 16 bit ALU core. Low Power Test Pattern (LP) Generator is programmable and able to produce pseudorandom test patterns. The programmability feature brings in selectiveness in toggling levels of test patterns. This helps to increase the error coverage gradient. This low power pattern generator consists of a pseudo random pattern generator (PSPR) which can be a linear feedback shift register or ring generator. The test pattern generator allows the production of binary sequences by devices with that selected toggling rate is defined as ‘Preselected toggling’ (PRESTO) activity. In this methodology, controls for operation of generator are selected automatically. Selection of all the controls is made simple and accurate for the tuning. Using this method fault coverage of test pattern generator can be improved as well as pattern count ratio gets improved. The proposed low power test compression method helps to get predictable test patterns. Here preselected toggling based logic BIST is used to get flexible and accurate test patterns hence high quality testing is achieved here with integration of PRESTO and LBIST method.

scholarly journals Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs

VLSI Design ◽  
2000 ◽  
Vol 11 (2) ◽  
pp. 149-159
Author(s):  
Chien-In Henry Chen ◽  
Yingjie Zhou
Keyword(s):  
Test Pattern ◽  
Linear Feedback ◽  
Random Pattern ◽  
Multiple Sequence ◽  
Linear Feedback Shift Registers ◽  
Synthesis Procedure ◽  
Feedback Shift Registers ◽  
Self Test ◽  
Random Patterns ◽  
Test Vectors

Recently a multiple-sequence test generator was presented based on two-dimensional linear feedback shift registers (2-D LFSR). This generator can generate a set of precomputed test vectors obtained by an ATPG tool for detecting random-pattern-resistant faults and particular hard-to-detect faults. In addition, it can generate better random patterns than a conventional LFSR. In this paper we describe an optimized BIST scheme which has a configurable 2-D LFSR structure. Starting from a set of stuck-at faults and a corresponding set of test vectors detecting these faults, the corresponding test pattern generator is determined automatically. A synthesis procedure of designing this test generator is presented. Experimental results show that the hardware overhead is considerably reduced compared with 2-D LFSR generators.

Weighted Cellular Automata Design for Test Pattern Generator Based on Genetic Algorithm

2013 ◽  
Vol 273 ◽  
pp. 840-844 ◽  
Author(s):  
En Min Tan ◽  
Qing Qing Li ◽  
Ji Gang Jiang
Keyword(s):  
Cellular Automata ◽  
Test Pattern ◽  
Pattern Generator ◽  
Fault Coverage ◽  
Test Design ◽  
Design For Test ◽  
Test Length ◽  
Vlsi Test ◽  
Self Test ◽  
Built In Self Test

In built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test length, fault coverage and test consumption, etc. A one-dimension hybrid cellular automata (CA) is used as the core of test pattern generator, with an optimization of its rules based on multi-objectives evolution algorithm. A certain rule which selected from the optimized rule set is adopted to form the weighted cellular automata, by the using of verilog HDL. Experiment results was obtained by simulation of some ISCAS’8n built-in self-test design for VLSI, test pattern generator should satisfy some multi-targets, such as test le5 benchmark circuits, and indicated that the test length was reduced obviously (at a ratio above 60%), without losing fault coverage (within a discrepancy of 3%); moreover, the power consumption would be decreased correspondingly.

Pseudoexhaustive test pattern generator with enhanced fault coverage

1988 ◽  
Vol 37 (4) ◽  
pp. 496-500 ◽  
Author(s):  
P. Golan ◽  
O. Novak ◽  
J. Hlavicka
Keyword(s):  
Test Pattern ◽  
Pattern Generator ◽  
Fault Coverage

scholarly journals A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration

2020 ◽  
Vol 9 (12) ◽  
pp. 217-220
Keyword(s):  
Field Programmable Gate Array ◽  
Test Pattern ◽  
Fault Coverage ◽  
Area Overhead ◽  
Field Programmable ◽  
Self Test ◽  
Gate Array ◽  
Built In Self Test ◽  
Pattern Generators ◽  
Logic Blocks

This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as complementary gates (AND/NAND, OR/NOR, XOR/XNOR) to successfully test the aforementioned faults. The proposed BIST structure when implemented on Xilinx Virtex-4 FPGA proved 100% fault coverage and minimized test configurations.

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