scholarly journals The Principles of Life Cycle Supporting System for Mission-Critical Systems

2018 ◽  
Vol 30 (1) ◽  
pp. 103-114 ◽  
Author(s):  
B.Α. Pozin
2018 ◽  
Author(s):  
Matthew Ridley ◽  
Carlos Otero ◽  
David Elliott ◽  
Xavier Merino

2018 ◽  
Author(s):  
Matthew Ridley ◽  
Carlos Otero ◽  
David Elliott ◽  
Xavier Merino

Author(s):  
В. Б. Бетелин ◽  
Д. А. Моргун

Происходящие в мире события свидетельствуют о возрастании угрозы перехвата управления системами с критической миссией (СКМ). Приводятся конкретные примеры инцидентов, один из них — массовые отключения электроэнергии в Венесуэле. Обосновывается необходимость разработки технологии создания цифровых систем управления, обеспечивающей парирование угрозы перехвата управления и нештатного функционирования систем с критической миссией. В основе этой технологии — концепция цифровых двойников объектов управления цифровых систем управления этими объектами, включая все аппаратные и программные компоненты, а также интеллектуальные средства самоконтроля и самокоррекции функционирования элементной базы, вычислительной и коммуникационной техники, базового и прикладного программного обеспечения. There is an ongoing threat of control interception in mission-critical systems (MCS). Specific examples of such incidents are presented, one of them is the massive power outages in Venezuela. We specify the reasons for creating an approach to developing digital control systems for MCS resistant to control interception and abnormal functioning. This technology is based on the digital twin concept. A twin represents all the hardware and software components, as includes smart tools for the hardware, core and application software self-monitoring and self-correction.  


Author(s):  
Sudha Srinivasan ◽  
D. S. Chauhan ◽  
Rekha R.

Field programmable gate arrays (FPGAs) are finding increasing number of applications in high integrity safety critical systems of aerospace and defence industry. Though FPGA design goes through various development processes, it is widely observed that the critical errors are observed in the final stages of development, thereby impacting time and cost. The risk of failure in complex embedded systems is overcome by using the independent verification and validation (IV&V) technique. Independent verification and validation (IV&V) of FPGA-based design is essential for evaluating the correctness, quality, and safety of the airborne embedded systems throughout the development life cycle and provides early detection and identification of risk elements. The process of IV&V and its planning needs to be initiated early in the development life cycle. This chapter describes the IV&V methodology for FPGA-based design during the development life cycle along with the certification process.


Author(s):  
Sergey Bratus ◽  
James Oakley ◽  
Ashwin Ramaswamy ◽  
Sean W. Smith ◽  
Michael E. Locasto

The mechanics of hot patching (the process of upgrading a program while it executes) remain understudied, even though it offers capabilities that act as practical benefits for both consumer and mission-critical systems. A reliable hot patching procedure would serve particularly well by reducing the downtime necessary for critical functionality or security upgrades. However, hot patching also carries the risk—real or perceived—of leaving the system in an inconsistent state, which leads many owners to forgo its benefits as too risky; for systems where availability is critical, this decision may result in leaving systems un-patched and vulnerable. In this paper, the authors present a novel method for hot patching ELF binaries that supports synchronized global data and code updates, and reasoning about the results of applying the hot patch. In this regard, the Patch Object format was developed to encode patches as a special type of ELF re-locatable object file. The authors then built a tool, Katana, which automatically creates these patch objects as a by-product of the standard source build process. Katana also allows an end-user to apply the Patch Objects to a running process.


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