Surface Characterisation of Si After HF Treatments and its Influence on the Dielectric Breakdown of Thermal Oxides

1992 ◽  
Vol 259 ◽  
Author(s):  
S. Verhaverbeke ◽  
J. Alay ◽  
P. Mertens ◽  
M. Meuris ◽  
M. Heyns ◽  
...  
Keyword(s):  
Contact Angle ◽  
Particle Deposition ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Surface Characterisation ◽  
Sensitive Measure ◽  
Degree Of Oxidation ◽  
Dipping Time ◽  
Metallic Contamination ◽  
Gate Oxide Integrity

ABSTRACTThe characteristics of the HF-treated Si-surface are investigated as a function of dipping time in dilute HF solutions. It is found that the contact angle is a very sensitive measure for the degree of oxidation of the Si-surface. The importance of obtaining a perfectly passivated surface in order to reduce the particle deposition on the surface is shown. HF-last cleans are found to be beneficial in terms of metallic contamination and gate oxide integrity. The importance of the loading ambient in furnaces is investigated after HF-treatments and RCA-cleans.

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

2009 ◽  
Author(s):  
Hua Younan ◽  
Chu Susan ◽  
Gui Dong ◽  
Mo Zhiqiang ◽  
Xing Zhenxiang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Dielectric ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Fault Isolation ◽  
Wafer Fabrication ◽  
Root Cause ◽  
Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

RCA and IMEC/SC2 Clean: Metallic Immunity and Gate Oxide Integrity

1997 ◽  
Vol 477 ◽  
Author(s):  
Weidong Chen ◽  
Tushar Dhayagude ◽  
Prasad Chaparala ◽  
Esin Demirlioglu ◽  
Mohsen Shenasa ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Process Line ◽  
Contamination Levels ◽  
Metallic Contamination ◽  
Gate Oxide Integrity

ABSTRACTDilute HF/RCA and IEMC/SC2 cleans have been evaluated on two process lines with different metallic contamination levels. VPD-DSE-TXRF and SPV techniques were used to monitor the metallic contamination. Gate oxide integrity(GOI) tests were performed on several structures. Both HF/RCA and IMEC/SC2 cleans have shown good Qbd and Ebd results for the clean process line. Lower Qbd and Ebd values were obtained for both cleans in the relatively contaminated process line. These results suggest that poor GOI is related to the metallic contamination in the oxide or at the SiO2/Si interface.

Effects of Silicon Ion Implantation upon Thin Gate Oxide Integrity

1992 ◽  
Vol 262 ◽  
Author(s):  
G. -S. Lee ◽  
J. -G. Park ◽  
S. -P. Choi ◽  
C. -H. Shin ◽  
Y. -B. Sun ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Dielectric Breakdown ◽  
Defect Density ◽  
Surface Region ◽  
Gate Oxide ◽  
Near Surface ◽  
Time Dependent Dielectric Breakdown ◽  
Thin Gate Oxide ◽  
Si Ion Implantation ◽  
Gate Oxide Integrity

ABSTRACTIn this study, using oxide breakdown voltage and time-dependent-dielectric breakdown measurements, thermal wave modulated reflectance and chemical etching/optical microscopy, we investigated effects of Si ion implantation upon formation of D-defects and thin gate oxide integrity. Our data show that addition of Si ion implantation with a dose of up to 1013 ions/cm2 improves oxide integrity if the implantation is done at a certain step just before sacrificial oxidation in the Mb DRAM process. However, no improvement in oxide integrity is observed when the same implantation is done on the virgin wafer surfaces at the start of the same Mb DRAM process. We discuss our hypothesis that the improvement in oxide integrity is due to a reduction in the D-defect density in the near-surface region of the wafer.

Effect of weak metallic contamination on silicon epitaxial layer and gate oxide integrity

2011 ◽  
Vol 46 (8) ◽  
pp. 805-808 ◽  
Author(s):  
D. Mello ◽  
C. Coccorese ◽  
E. Ferlito ◽  
G. Sciuto ◽  
R. Ricciari ◽  
...  
Keyword(s):  
Epitaxial Layer ◽  
Gate Oxide ◽  
Silicon Epitaxial Layer ◽  
Metallic Contamination ◽  
Gate Oxide Integrity

Study of Time Dependent Dielectric Breakdown Distribution in Ultrathin Gate Oxide

2007 ◽  
Vol 46 (No. 28) ◽  
pp. L691-L692 ◽  
Author(s):  
Takashi Miyakawa ◽  
Tsutomu Ichiki ◽  
Junichi Mitsuhashi ◽  
Kazutoshi Miyamoto ◽  
Tetsuo Tada ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Time Dependent ◽  
Time Dependent Dielectric Breakdown

Materials, device and gate oxide integrity evaluation of SIMOX and bonded SOI wafers

2002 ◽  
Author(s):  
S.R. Wilson ◽  
T. Wetteroth ◽  
S. Hong ◽  
H. Shin ◽  
B.-Y. Hwang ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Gate Oxide Integrity

Gate oxide integrity on ITOX-SIMOX substrates and influence of test device geometry on characterization

2001 ◽  
Vol 48 (2) ◽  
pp. 307-315 ◽  
Author(s):  
K. Kawamura ◽  
H. Deai ◽  
H. Sakamoto ◽  
T. Yano ◽  
I. Hamaguchi ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Test Device ◽  
Device Geometry ◽  
Gate Oxide Integrity
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