A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Electrical Characterization of Different Failure Modes in Sub-100 nm Devices Using Nanoprobing Technique

The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.

Laser Timing Probe with Frequency Mapping for Locating Signal Maxima

A Laser Timing Probe (LTP) system which uses a noninvasive 1.3 µm continuous wave (CW) laser with frequency mapping and single point measurement capabilities is described. The frequency mapping modes facilitate the localization of signal maxima for subsequent single point measurements. Measurements of waveforms with long delays and 50 ps response time from NMOS and PMOS transistors are also shown.

An Advanced Reliability Improvement and Failure Analysis Approach to Thermal Stress Issues in IC Packages

A new approach to reliability improvement and failure analysis on ICs is introduced, involving a specifically developed tool for Topography and Deformation Measurement (TDM) under thermal stress conditions. Applications are presented including delamination risk or bad solderability assessment on BGAs during JEDEC type reflow cycles.

Credits

Listings of the EDFAS 2009-2010 Board of Directors, the ISTFA 2009 Organizing Committee and Activities Chairs, and other contributors and committee members.

Conductive Filament Formation in Printed Circuit Boards – Effects of Reflow Conditions and Flame Retardants

Failures in printed circuit boards account for a significant percentage of field returns in electronic products and systems. Conductive filament formation is an electrochemical process that requires the transport of a metal through or across a nonmetallic medium under the influence of an applied electric field. With the advent of lead-free initiatives, boards are being exposed to higher temperatures during lead-free solder processing. This can weaken the glass-fiber bonding, thus enhancing conductive filament formation. The effect of the inclusion of halogen-free flame retardants on conductive filament formation in printed circuit boards is also not completely understood. Previous studies, along with analysis and examinations conducted on printed circuit boards with failure sites that were due to conductive filament formation, have shown that the conductive path is typically formed along the delaminated fiber glass and epoxy resin interfaces. This paper is a result of a year-long study on the effects of reflow temperatures, halogen-free flame retardants, glass reinforcement weave style, and conductor spacing on times to failure due to conductive filament formation.

Degradation Analysis of Thick Film Chip Resistors

Negative resistance drift in thick film chip resistors in high temperature and high humidity application conditions was investigated. This paper reports on the investigation of possible causes including formation of current leakage paths on the printed circuit board, delamination between the resistor protective coating and laser trim, and the possibility of silver migration or copper dendrite formation. Analysis was performed on a set of circuit boards exhibiting failures due to this phenomenon. Electrical tests after mechanical and chemical modifications showed that the drift was most likely caused by moisture ingress that created a conductive path across the laser trim.

Picosecond Single-Photon and Femtosecond Two-Photon Pulsed Laser Stimulation for IC Characterization and Failure Analysis

This paper presents the use of pulsed laser stimulation with picosecond and femtosecond laser pulses. We first discuss the resolution improvement that can be expected when using ultrashort laser pulses. Two case studies are then presented to illustrate the possibilities of the pulsed laser photoelectric stimulation in picosecond single-photon and femtosecond two-photon modes.

Effectiveness of Nanoprober in Detecting Single/Multiple Bit Flash Data Gain & Data Loss Failures

This paper discusses the physics, definitions, and nanoprobing flow of a flash bit memory. In addition, a case study showing the effectiveness of nanoprobing in detecting the Single Bit Fail Data Gain and Data Loss in Flash Memory is also discussed. The paper also includes cases where no passive voltage contrast was observed at the SEM and no leakage was observed at AFM, yet the units failing SBF DG, SBF DL and depletion, were detected by nanoprobing of the single bit. The major finding of this paper is a way to resolve data gain, data loss, and depletion failures of flash memory by nanoprobing procedure, despite no PVC seen at the SEM and no leakage seen at the AFM.

Decapsulation Techniques for Cu Wire Bonding Package

This paper presents decapsulation solutions for devices bonded with Cu wire. By removing mold compound to a thin layer using a laser ablation tool, Cu wire bonded packages are decapsulated using wet chemical etching by controlling the etch time and temperature. Further, the paper investigates the possibilities of decapsulating Cu wire bonded devices using full wet chemical etches without the facilitation of laser ablation removing much of mold compound. Additional discussion on reliability concerns when evaluating Cu wirebond devices is addressed here. The lack of understanding of the reliability of Cu wire bonded packages creates a challenge to the FA engineer as they must develop techniques to help understanding the reliability issue associated with Cu wire bonding devices. More research and analysis are ongoing to develop appropriate analysis methods and techniques to support the Cu wire bonding device technology in the lab.