An optimization method for NBTI-aware design of domino logic circuits in nano-scale CMOS

Masaoud Houshmand Kaffashian; Reza Lotfi; Khalil Mafinezhadand; Hamid Mahmoodi

doi:10.1587/elex.8.1406

An optimization method for NBTI-aware design of domino logic circuits in nano-scale CMOS

IEICE Electronics Express ◽

10.1587/elex.8.1406 ◽

2011 ◽

Vol 8 (17) ◽

pp. 1406-1411 ◽

Cited By ~ 4

Author(s):

Masaoud Houshmand Kaffashian ◽

Reza Lotfi ◽

Khalil Mafinezhadand ◽

Hamid Mahmoodi

Keyword(s):

Optimization Method ◽

Logic Circuits ◽

Domino Logic ◽

Nano Scale

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An optimization method for NBTI-aware design of domino logic circuits in nano-scale CMOS: errata

IEICE Electronics Express ◽

10.1587/elex.8.1640 ◽

2011 ◽

Vol 8 (19) ◽

pp. 1640-1640

Keyword(s):

Optimization Method ◽

Logic Circuits ◽

Domino Logic ◽

Nano Scale

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Impact of NBTI on performance of domino logic circuits in nano-scale CMOS

Microelectronics Journal ◽

10.1016/j.mejo.2011.09.009 ◽

2011 ◽

Cited By ~ 2

Author(s):

M. Houshmand Kaffashian ◽

R. Lotfi ◽

K. Mafinezhad ◽

H. Mahmoodi

Keyword(s):

Logic Circuits ◽

Domino Logic ◽

Nano Scale

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Design Of Domino Logic Circuits By An Optimization Method

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. ◽

10.1109/mixdes.2006.1706580 ◽

2006 ◽

Author(s):

A.S. Seyedi ◽

S.H. Rasouli ◽

A. Amirabadi ◽

A. Afzali-Kusha ◽

C. Lucas ◽

...

Keyword(s):

Optimization Method ◽

Logic Circuits ◽

Domino Logic

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ONOFIC Pull-Up Approach in Domino Logic Circuits Using FinFET for Subthreshold Leakage Reduction

Circuits Systems and Signal Processing ◽

10.1007/s00034-018-0980-8 ◽

2018 ◽

Vol 38 (6) ◽

pp. 2564-2587

Author(s):

Vijay Kumar Magraiya ◽

Tarun Kumar Gupta

Keyword(s):

Logic Circuits ◽

Domino Logic ◽

Leakage Reduction ◽

Subthreshold Leakage

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Charge sharing fault detection for CMOS domino logic circuits

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) ◽

10.1109/dftvs.1999.802872 ◽

2003 ◽

Cited By ~ 8

Author(s):

C.H. Cheng ◽

S.C. Chang ◽

J.S. Wang ◽

W.B. Jone

Keyword(s):

Fault Detection ◽

Logic Circuits ◽

Charge Sharing ◽

Domino Logic

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Performance evaluation of domino logic circuits for wide fan-in gates with FinFET

Microsystem Technologies ◽

10.1007/s00542-017-3691-3 ◽

2018 ◽

Vol 24 (8) ◽

pp. 3341-3348 ◽

Cited By ~ 4

Author(s):

Ajay Kumar Dadoria ◽

Kavita Khare ◽

Uday Panwar ◽

Anita Jain

Keyword(s):

Performance Evaluation ◽

Logic Circuits ◽

Domino Logic

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A 4:1 Multiplexer using dual chirality CNTFET-based domino logic in nano-scale technology

International Journal of Electronics ◽

10.1080/00207217.2019.1663942 ◽

2019 ◽

Vol 107 (4) ◽

pp. 513-541

Author(s):

Sandeep Garg ◽

Tarun K. Gupta ◽

Amit K. Pandey

Keyword(s):

Domino Logic ◽

Nano Scale

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A Technique for Designing Totally Self-Checking Domino Logic Circuits

Sixth International Symposium on Quality of Electronic Design (ISQED'05) ◽

10.1109/isqed.2005.14 ◽

2005 ◽

Author(s):

C.K. Tang ◽

P.K. Lala ◽

J.P. Parkerson

Keyword(s):

Logic Circuits ◽

Domino Logic

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Mixed-swing methodology for domino logic circuits

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169) ◽

10.1109/cicc.2001.929729 ◽

2002 ◽

Author(s):

A. Rave ◽

L.R. Carley

Keyword(s):

Logic Circuits ◽

Domino Logic

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PVT variations aware low leakage DOIND approach for nanoscale domino logic circuits

2015 IEEE Power, Communication and Information Technology Conference (PCITC) ◽

10.1109/pcitc.2015.7438222 ◽

2015 ◽

Cited By ~ 2

Author(s):

Ambika Prasad Shah ◽

Vaibhav Neema ◽

Shreeniwas Daulatabad

Keyword(s):

Logic Circuits ◽

Domino Logic ◽

Low Leakage ◽

Pvt Variations

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