scholarly journals Constant-coefficient FIR filters based on residue number system arithmetic

2012 ◽  
Vol 9 (3) ◽  
pp. 325-342 ◽  
Author(s):  
Negovan Stamenkovic ◽  
Vladica Stojanovic
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Finite Impulse Response ◽  
Number System ◽  
Residue Number System ◽  
Fir Filter ◽  
Fir Filters ◽  
Residue Number ◽  
Low Power Dissipation ◽  
Residue Arithmetic

In this paper, the design of a Finite Impulse Response (FIR) filter based on the residue number system (RNS) is presented. We chose to implement it in the (RNS), because the RNS offers high speed and low power dissipation. This architecture is based on the single RNS multiplier-accumulator (MAC) unit. The three moduli set {2n+1,2n,2n-1}, which avoids 2n+1 modulus, is used to design FIR filter. A numerical example illustrates the principles of residue encoding, residue arithmetic, and residue decoding for FIR filters.

scholarly journals Digital FIR filter architecture based on the residue number system

2009 ◽  
Vol 22 (1) ◽  
pp. 125-140 ◽  
Author(s):  
Negovan Stamenkovic
Keyword(s):  
High Speed ◽  
Direct Synthesis ◽  
Number System ◽  
Residue Number System ◽  
Fir Filter ◽  
Fir Filters ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Filter Architecture ◽  
Residue Number

In this paper, architecture of residue number system used in FIR filters, is presented. For many years residue number coding has been recognized as a system which provides capability for implementation of a high speed addition and multiplication. These advantages of residue number system coding for the high speed FIR filters design results from the fact that an digital FIR filter requires only addition and multiplication. The proposed FIR filter architecture is performed as series of modulo multiplication and accumulation across each modulo. A numerical example illustrates the principles of FIR filtering of an 32 order low pass filter. This architecture is compared with FIR filters direct synthesis. .

scholarly journals FPGA Implementation of high speed-low energy RNS based Reconfigurable-FIR Filter for Cognitive Radio Applications

2021 ◽  
Vol 16 ◽  
pp. 278-293
Author(s):  
C. Srinivasa Murthy ◽  
K. Sridevi
Keyword(s):  
Finite Impulse Response ◽  
Number System ◽  
Residue Number System ◽  
Fir Filter ◽  
Data Partitioning ◽  
Input Word ◽  
Trade Off ◽  
Filter Length ◽  
Reverse Conversion ◽  
Residue Number

The Finite impulse response (FIR) filter is prominently employed in many digital signal processing (DSP) systems for various applications. In this paper, we present a high-performance RNS based FIR filter design for filtration in SDR applications. In general, the residue number system (RNS) gives significant metrics over FIR implementation with its inherent parallelism and data partitioning mechanism. But with increased bit width cause considerable performance trade-off due to both residue computation and reverse conversion. In this paper optimized Residue Number System (RNS) arithmetic is proposed which includes distributed arithmetic based residue computation during RNS multiplication followed by speculative delay optimized reverse computation to mitigate the FIR filter trade-off characteristics with filter length. The proposed RNS design utilizes built-in RAMs block present in the devices of FPGA to accomplish the process of reverse conversion and to store pre-computational values. A distinctive feature of the proposed FIR filter implementation with core optimized RNS is to minimize hardware complexity overhead with the improved operating speed. Initially, fetal audio signal detection is carried out to validate the functionality of FIR filter core and FPGA hardware synthesis is carried out for various input word size and FIR length. From the experimental, it is proved that the trade-off exists in conventional RNS FIR over filter length is narrow down along with considerable complexity reduction with our proposed optimized RNS system.

EFFICIENT RNS-BASED DESIGN OF PROGRAMMABLE FIR FILTERS TARGETING FPL TECHNOLOGY

2005 ◽  
Vol 14 (01) ◽  
pp. 165-177 ◽  
Author(s):  
JAVIER RAMÍREZ ◽  
UWE MEYER-BÄSE ◽  
ANTONIO GARCÍA
Keyword(s):  
High Performance ◽  
Digital Signal ◽  
Number System ◽  
Low Complexity ◽  
Residue Number System ◽  
Quadratic Residue ◽  
Fir Filter ◽  
Efficient Implementation ◽  
Fir Filters ◽  
Residue Number

FIR filters are routinely used in the implementation of modern digital signal processing systems. Their efficient implementation using commercially available VLSI technology is a subject of continuous study and development. This paper presents the residue number system (RNS) implementation of reduced-complexity and high-performance FIR filters, using modern Altera APEX20K field-programmable logic (FPL) devices. Index arithmetic over Galois fields and the Quadratic Residue Number System (QRNS), along with a selection of a small wordwidth modulus set, are the keys for attaining low complexity and high throughput in real and complex FIR filters. RNS–FPL merged FIR filters demonstrated its superiority when compared to 2C (two's complement) filters, being about 65% faster and requiring fewer logic elements for most study cases. Special attention was paid to an efficient implementation of the multi-operand modulo adders. The replacement of a classical modulo adder tree by a binary adder with extended precision followed by a single modulo reduction stage reduced area requirements by 10% for a 32-tap FIR filter. On the other hand, an index arithmetic QRNS-based complex FIR filter yielded up to 60% performance improvement over a three-multiplier-per-tap 2C filter, while requiring fewer LEs for filters having more than eight taps. Particularly, a 32-tap filter needed 24% LEs less than the classical design.

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