Design of a high speed reverse converter for a new 4-moduli set residue number system

2003 ◽  
Author(s):  
Bin Cao ◽  
T. Srikanthan ◽  
Chip-Hong Chang
Keyword(s):  
High Speed ◽  
Number System ◽  
Residue Number System ◽  
Reverse Converter ◽  
Residue Number

scholarly journals Reverse convertor design for the 4-moduli set {2ⁿ -1,2ⁿ, 2ⁿ +1,2²ⁿ+¹ -1} based on the mixed-radix conversion

2011 ◽  
Vol 24 (1) ◽  
pp. 89-103
Author(s):  
Negovan Stamenkovic ◽  
Bojan Jovanovic
Keyword(s):  
High Speed ◽  
Number System ◽  
Residue Number System ◽  
Hardware Architecture ◽  
Reverse Conversion ◽  
Reverse Converter ◽  
Mixed Radix Conversion ◽  
Residue Number

The residue number system (RNS) is an integer system capable of supporting high speed concurrent arithmetic. One of the most important consideration when designing RNS system is reverse conversion. The reverse converter for recently proposed for the four-moduli set {2? -1,2?, 2? +1,2??+? -1} is based on new Chinese remainder theorems II (New CRT-II) [6]. This paper presents an alternative architecture derived by Mixed-Radix conversion for this four-moduli set. Due to the using simple multiplicative inverses of the proposed moduli set, it can considerably reduce the complexity of the RNS to binary converter based on the Mixed-Radix conversion. The hardware architecture for the proposed converter is based on the adders and subtractors, without the needed ROM or multipliers.

scholarly journals Constant-coefficient FIR filters based on residue number system arithmetic

2012 ◽  
Vol 9 (3) ◽  
pp. 325-342 ◽  
Author(s):  
Negovan Stamenkovic ◽  
Vladica Stojanovic
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Finite Impulse Response ◽  
Number System ◽  
Residue Number System ◽  
Fir Filter ◽  
Fir Filters ◽  
Residue Number ◽  
Low Power Dissipation ◽  
Residue Arithmetic

In this paper, the design of a Finite Impulse Response (FIR) filter based on the residue number system (RNS) is presented. We chose to implement it in the (RNS), because the RNS offers high speed and low power dissipation. This architecture is based on the single RNS multiplier-accumulator (MAC) unit. The three moduli set {2n+1,2n,2n-1}, which avoids 2n+1 modulus, is used to design FIR filter. A numerical example illustrates the principles of residue encoding, residue arithmetic, and residue decoding for FIR filters.

A MEMORYLESS REVERSE CONVERTER FOR THE 4-MODULI SUPERSET {2n - 1, 2n, 2n + 1, 2n + 1 - 1}

2000 ◽  
Vol 10 (01n02) ◽  
pp. 85-99 ◽  
Author(s):  
A. P VINOD ◽  
A. BENJAMIN PREMKUMAR
Keyword(s):  
High Performance ◽  
Dynamic Range ◽  
Number System ◽  
Residue Number System ◽  
Main Challenge ◽  
Reverse Converter ◽  
Residue Number ◽  
Compensation Technique ◽  
The Common ◽  
Performance Computing

This paper presents a residue number system to binary converter in the four moduli set {2n - 1, 2n, 2n + 1, 2n + 1 - 1}, valid for even values of n. This moduli set is an extension of the popular set {2n - 1, 2n + 1}. The number theoretic properties of the moduli set of the form 2n ± 1 are exploited to design the converter. The main challenge of dealing with fractions in Residue Number System is overcome by using the fraction compensation technique. A hardware implementation using only adders is also proposed. When compared to the common three moduli reverse converters, this four moduli converter offers a larger dynamic range and higher parallelism, which makes it useful for high performance computing.

A high-speed division algorithm in residue number system using parity-checking technique

2004 ◽  
Vol 81 (6) ◽  
pp. 775-780 ◽  
Author(s):  
Jen-Ho Yang * ◽  
Chin-Chen Chang ◽  
Chien-Yuan Chen ‡
Keyword(s):  
High Speed ◽  
Number System ◽  
Residue Number System ◽  
Division Algorithm ◽  
Residue Number

scholarly journals Design and Analysis of 32-bit Reverse Converter based on low power Parallel Prefix Adder

2019 ◽  
Vol 9 (1) ◽  
pp. 3028-3031
Keyword(s):  
Low Power ◽  
High Speed ◽  
Digital Signal ◽  
Number System ◽  
Residue Number System ◽  
Propagation Delay ◽  
Main Role ◽  
Reverse Conversion ◽  
Reverse Converter ◽  
Parallel Prefix

The Residue Number System (RNS) based reverse converter can play as main role in Parallel arithmetic operations of Digital Signal Processing (DSP) applications and VLSI technologies. Normally, by the use of carry adders, the reverse conversion design gives high delay and high power consumption. Due to resolve of above problem, the design of reverse converter is proposed by the use of familiar high speed (less propagation delay) Parallel Prefix - Kogge Stone Adder (PP- KSA). This paper describes the design of 32-bit Reverse converter with regular PP-KSA and proposed MUX (Multiplex) logic of PP-KSA with Hybrid Modular Parallel Prefix structure (HMPE) separately. In addition to that, the performance of that designs are analysed based on area, delay and power independently. The Performance results of proposed MUX logic of PP-KSA Reverse converter design yields low power than the other design which uses the regular PP-KSA. The simulation and synthesis effects can be done in Xilinx ISE 14.2i tool.

Interval Estimation of Relative Values in Residue Number System

2017 ◽  
Vol 27 (01) ◽  
pp. 1850004 ◽  
Author(s):  
Konstantin Isupov ◽  
Vladimir Knyazkov
Keyword(s):  
High Speed ◽  
Interval Estimation ◽  
Number System ◽  
Residue Number System ◽  
Floating Point ◽  
Limiting Factor ◽  
Small Integer ◽  
Magnitude Comparison ◽  
Mixed Radix Conversion ◽  
Residue Number

Residue number system (RNS), due to its carry-free nature, is popular in many applications of high-speed computer arithmetic, especially in digital signal processing and cryptography. However, the main limiting factor of RNS is a high complexity of such operations as magnitude comparison, sign determination and overflow detection. These operations have, for many years, been a major obstacle to more widespread use of parallel residue arithmetic. This paper presents a new efficient method to perform these operations, which is based on computation and analysis of the interval estimation for the relative value of an RNS number. The estimation, which is called the interval floating-point characteristic (IFC), is represented by two directed rounded bounds that are fixed-precision numbers. Generally, the time complexities of serial and parallel computations of IFC are linear and logarithmic functions of the size of the moduli set, respectively. The new method requires only small-integer and fixed-precision floating-point operations and focuses on arbitrary moduli sets with large dynamic ranges ([Formula: see text]). Experiments indicate that the performance of the proposed method is significantly higher than that of methods based on Mixed-Radix Conversion.

Sign in / Sign up

Export Citation Format

Share Document