SIMULATION BASED LOW POWER TEST GENERATION FOR CROSSTALK DELAY FAULTS

2011 ◽  
Vol 31 (3) ◽  
Author(s):  
Jayanthy Soundararajan ◽  
Bhuvaneswari M. Chinnadurai
Keyword(s):  
Low Power ◽  
Test Generation ◽  
Delay Faults ◽  
Power Test ◽  
Low Power Test ◽  
Simulation Based

Low Power Test Generation for Path Delay Faults

2005 ◽  
Vol 1 (2) ◽  
pp. 194-205
Author(s):  
M. M. Vaseekar Kumar ◽  
S. Tragoudas
Keyword(s):  
Low Power ◽  
Test Generation ◽  
Delay Faults ◽  
Path Delay ◽  
Path Delay Faults ◽  
Power Test ◽  
Low Power Test

A Probabilistic and Constraint Based Approach for Low Power Test Generation

2012 ◽  
Author(s):  
Hossein Sabaghian-Bidgoli ◽  
Majid Namaki-Shoushtari ◽  
Zainalabedin Navabi
Keyword(s):  
Low Power ◽  
Test Generation ◽  
Power Test ◽  
Low Power Test

Search Space Reduction for Low-Power Test Generation

2013 ◽  
Author(s):  
Kohei Miyase ◽  
Matthias Sauer ◽  
Berund Becker ◽  
Xiaoqing Wen ◽  
Seiji Kajihara
Keyword(s):  
Low Power ◽  
Test Generation ◽  
Search Space ◽  
Power Test ◽  
Space Reduction ◽  
Low Power Test ◽  
Search Space Reduction

Access-in-turn test architecture for low-power test application

2016 ◽  
Vol 104 (3) ◽  
pp. 433-441 ◽  
Author(s):  
Weizheng Wang ◽  
JinCheng Wang ◽  
Zengyun Wang ◽  
Lingyun Xiang
Keyword(s):  
Low Power ◽  
Power Test ◽  
Low Power Test ◽  
Test Application ◽  
Test Architecture
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