scholarly journals Modelling Gene-Protein-Reaction Associations on an FPGA

2019 ◽  
Author(s):  
Macauley Coggins
Keyword(s):  
Metabolic Model ◽  
Logic Device ◽  
Description Language ◽  
Metabolic Modelling ◽  
Quartus Ii ◽  
Hardware Description ◽  
Design Software ◽  
Genome Scale ◽  
The Relationship ◽  
Protein Reaction

Genome-Scale metabolic models have proven to be incredibly useful.Allowing researchers to model cellular functionality based upon gene expression. However as the number of genes and reactions increases it can become computationally demanding. The first step in genome-scale metabolic modelling is to model the relationship between genes and reactions in the form of Gene-Protein-Reaction Associations (GPRA). In this research we have developed a way to model GPRAs on an Altera Cyclone II FPGA using Quartus II programmable logic device design software and the VHDL hardware description language. The model consisting of 7 genes and 7 reactions was implemented using 7 combinational functions and 14 I/O pins. This model will be the first step towards creating a full genome scale metabolic model on FPGA devices which we will be fully investigating in future studies.

scholarly journals Modelling Gene-Protein-Reaction Associations on an FPGA

2019 ◽  
Author(s):  
Macauley Coggins
Keyword(s):  
Metabolic Model ◽  
Logic Device ◽  
Description Language ◽  
Metabolic Modelling ◽  
Quartus Ii ◽  
Hardware Description ◽  
Design Software ◽  
Genome Scale ◽  
The Relationship ◽  
Protein Reaction

AbstractGenome-Scale metabolic models have proven to be incredibly useful. Allowing researchers to model cellular functionality based upon gene expression. However as the number of genes and reactions increases it can become computationally demanding. The first step in genome-scale metabolic modelling is to model the relationship between genes and reactions in the form of Gene-Protein-Reaction Associations (GPRA). In this research we have developed a way to model GPRAs on an Altera Cyclone II FPGA using Quartus II programmable logic device design software and the VHDL hardware description language. The model consisting of 7 genes and 7 reactions was implemented using 7 combinational functions and 14 I/O pins. This model will be the first step towards creating a full genome scale metabolic model on FPGA devices which we will be fully investigating in future studies.

scholarly journals Framework and resource for more than 11,000 gene-transcript-protein-reaction associations in human metabolism

2017 ◽  
Vol 114 (45) ◽  
pp. E9740-E9749 ◽  
Author(s):  
Jae Yong Ryu ◽  
Hyun Uk Kim ◽  
Sang Yup Lee
Keyword(s):  
Transcript Level ◽  
Metabolic Model ◽  
Protein Isoforms ◽  
Gene Transcript ◽  
Human Metabolism ◽  
Functional Roles ◽  
Metabolic Genes ◽  
Level Data ◽  
Genome Scale ◽  
Protein Reaction

Alternative splicing plays important roles in generating different transcripts from one gene, and consequently various protein isoforms. However, there has been no systematic approach that facilitates characterizing functional roles of protein isoforms in the context of the entire human metabolism. Here, we present a systematic framework for the generation of gene-transcript-protein-reaction associations (GeTPRA) in the human metabolism. The framework in this study generated 11,415 GeTPRA corresponding to 1,106 metabolic genes for both principal and nonprincipal transcripts (PTs and NPTs) of metabolic genes. The framework further evaluates GeTPRA, using a human genome-scale metabolic model (GEM) that is biochemically consistent and transcript-level data compatible, and subsequently updates the human GEM. A generic human GEM, Recon 2M.1, was developed for this purpose, and subsequently updated to Recon 2M.2 through the framework. Both PTs and NPTs of metabolic genes were considered in the framework based on prior analyses of 446 personal RNA-Seq data and 1,784 personal GEMs reconstructed using Recon 2M.1. The framework and the GeTPRA will contribute to better understanding human metabolism at the systems level and enable further medical applications.

Research and Design of Beamforming Device of SLC-LSCMA Algorithm Based on FPGA

2013 ◽  
Vol 347-350 ◽  
pp. 1677-1681
Author(s):  
Qing Fang Zhou ◽  
Yan Yan Yu ◽  
Lei Wang ◽  
Jun Yang
Keyword(s):  
Least Squares ◽  
Satellite Communications ◽  
Clock Frequency ◽  
Verilog Hdl ◽  
Description Language ◽  
Quartus Ii ◽  
Hardware Description ◽  
Timing Simulation ◽  
Array Beamforming ◽  
Research And Design

In this paper,we design a uniform circular array beamforming device of 16 yuan based on the least squares SLC-LSCMA algorithm (based on the linear subspace constrained least squares cma) high stability and rapid convergence for the foundation. The design of the complete beam-forming the SLC-LSCMA algorithm by plural, time-multiplier and accumulators, which uses less resources and faster than the traditional algorithm. The beamforming device uses hardware description language of Verilog HDL , and wires on the QUARTUS II 8.0. Finally the beamforming device is downloaded to the Alteras EP2C35F672C6, and its timing simulation can be run properly in the 50MHz clock frequency. This design can be widely used in mobile communication and satellite communications.

Design and Implementation of the Infrared Remote-Controlled Digital Clock Based on FPGA

2015 ◽  
Vol 738-739 ◽  
pp. 1266-1269
Author(s):  
Jun Yang ◽  
Hong Ye Li ◽  
Long Liu
Keyword(s):  
Simple Structure ◽  
Digital Circuit ◽  
Description Language ◽  
Digital Clock ◽  
Development Cycle ◽  
Short Development Cycle ◽  
Quartus Ii ◽  
Function Modules ◽  
Hardware Description ◽  
And Function

The digital clock is a clock designed by digital circuit. Now, there are some limitations in the use and regulation of the digital clock in the large square. In this paper, the infrared remote-controlled digital clock based on FPGA can solve this problem well. This digital clock is composed of three parts: infrared remote control module, main circuit of the digital clock and function modules. And it is designed by the VHDL hardware description language, in the Quartus II software development environment.In addition, the digital clock has many extended functions, such as the hour timekeeping, alarm clock and temperature measuring. Besides, it has many advantages, including stable system , simple structure, short development cycle, fast speed and the strong usability.

The Design and Implementation of a High-Speed Parallel AES Crypto-Chip

2012 ◽  
Vol 468-471 ◽  
pp. 1721-1725 ◽  
Author(s):  
Jun Yang ◽  
Wei Ping Zhang ◽  
Ping Ping Shu ◽  
Xiao Jun Wang ◽  
Ga Zhao ◽  
...  
Keyword(s):  
High Speed ◽  
Language Use ◽  
Processing Unit ◽  
Description Language ◽  
Development Platform ◽  
Quartus Ii ◽  
Time Requirements ◽  
Hardware Description ◽  
Network Transmission ◽  
Encryption Decryption

This paper direct to security and real-time requirements in high-speed network transmission processing, based on SOPC technology, design a High throughput AES encryption/ decryption processing unit with pipelining. The design goal is to optimize the hardware structure and improve the throughput, S-box design and parallel processing structure. Compared with traditional AES crypto-chip has faster rate with encryption and less consumption of resources advantages. This design adopts VHDL hardware description language, use Quartus II 8.0 for the synthesis and routing, and this processing unit is packaged an independent IP core, attached to the Altera provided the Nios II system, finally download and test validation on the DE2 development platform.

scholarly journals An Effective FPGA Solver on Probability Distribution and Preprocessing

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 333 ◽  
Author(s):  
Kefan Ma ◽  
Liquan Xiao ◽  
Jianmin Zhang
Keyword(s):  
Probability Distribution ◽  
Boolean Satisfiability ◽  
Hardware Description Language ◽  
Selection Strategy ◽  
Programmable Logic ◽  
Logic Device ◽  
Description Language ◽  
Sat Solver ◽  
Hardware Description ◽  
Novel Algorithm

The Boolean satisfiability (SAT) problem is the key problem in computer theory and application. A novel algorithm is introduced to implement a SLS hardware solver called probSAT+. The algorithm has no complex heuristic, and it only depends on the concepts of preprocessing technology, probability distribution and centralized search. Through constraining the initial assignments of the variables, the number of flipped variables was reduced while the solver finding a solution. Moreover, the algorithm no longer adopts some non-continuous if-then-else decisions, but depends on a single continuous function f(x,v). The flipping probability is not obtained by complex calculations, instead being selected by looking up tables, which effectively improves the performance of the solver. As far as we know, the probability distribution selection strategy descripted by hardware description language is firstly adopted by hardware SAT solver, which can be easily transplanted to any programmable logic device. The experimental results show that the probSAT+ solver is generally lower than the advanced software solver in the number of flips (up to 9.8 × 10 6 ), and the speedup is approximately 2.6 times with single thread, which shows that the probSAT+ has better results with fewer variables flipping times when a solution can be found. In addition, the success ratio of the solver in finding a solution of the problem in a suitable time is 100%.

IP Core Design of 8253 Based on Quartus II

2013 ◽  
Vol 380-384 ◽  
pp. 2941-2944
Author(s):  
Hai Yan Zhang
Keyword(s):  
Software Development ◽  
Hardware Description Language ◽  
Logic Design ◽  
Ip Core ◽  
Description Language ◽  
Development Platform ◽  
Quartus Ii ◽  
Hardware Description ◽  
Gate Array

Provided by ALTERA FPGA/CPLD Quartus II development software development platform. programmable timer/counter 8253s functions and internal circuitry as the basis, combined with programmable gate array (FPGA) products FLEX10KE characteristics, using VHDL hardware description language and schematic Figure two ways 8253 for hierarchical, modular, parameterized logic design. The completed design will be configured to the chip of FLEX10KE,and Proved to be correct.

The Design of Digital Filter Based on DSP Builder

2014 ◽  
Vol 602-605 ◽  
pp. 2641-2644
Author(s):  
Xiao Li Hu ◽  
Li Ding ◽  
Zhi Gang Zhang
Keyword(s):  
Digital Filter ◽  
Hardware Description Language ◽  
Description Language ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Paper Model ◽  
Dsp Builder ◽  
Quartus Ii ◽  
Low Pass ◽  
Hardware Description

This paper model digital FIR low-pass by using the Toolbox of the DSP Builder in MATLAB and convert to VHDL hardware description language, compile and simulation through QUARTUS II software automatically, download and verified by EPF10K20RC208-4.The design combine MATLAB software with FPGA hardware organic ally and completes the transplant of the FIR low-pass filter.

scholarly journals Study of Data Security Algorithms using Verilog HDL

2015 ◽  
Vol 5 (5) ◽  
pp. 1092
Author(s):  
M. Sumathi ◽  
D. Nirmala ◽  
R. Immanuel Rajkumar
Keyword(s):  
Performance Evaluation ◽  
Data Security ◽  
Hardware Description Language ◽  
Performance Study ◽  
Verilog Hdl ◽  
Description Language ◽  
Quartus Ii ◽  
Encryption And Decryption ◽  
Different Types ◽  
Hardware Description

This paper describes an overview of data security algorithms and its performance evaluation. AES, RC5 and SHA algorithms have been taken under this study. Three different types of security algorithms used to analyze the performance study. The designs were implemented in Quartus-II software. The results obtained for encryption and decryption procedures show a significant improvement on the performance of the three algorithms. In this paper, 128-bit AES, 64-bit of RC5 and 512-bit of SHA256 encryption and Decryption has been made using Verilog Hardware Description Language and simulated using ModelSim.

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