FPGA-based Implementation of SHA-256 with Improvement of Throughput using Unfolding Transformation

Security has grown in importance as a study issue in recent years. Several cryptographic algorithms have been created to increase the performance of these information-protecting methods. One of the cryptography categories is a hash function. This paper proposes the implementation of the SHA-256 (Secure Hash Algorithm-256) hash function. The unfolding transformation approach was presented in this study to enhance the throughput of the SHA-256 design. The unfolding method is employed in the hash function by producing the hash value output based on modifying the SHA-256 structure. In this unfolding method, SHA-256 decreases the number of clock cycles required for traditional architecture by a factor of two, from 64 to 34 because of the delay. To put it another way, one cycle of the SHA-256 design can generate up to four parallel inputs for the output. As a result, the throughput of the SHA-256 design can be improved by reducing the number of cycles by 16 cycles. ModelSim was used to validate the output simulations created in Verilog code. The SHA-256 hash function factor four hardware implementation was successfully tested using the Altera DE2-115 FPGA board. According to timing simulation findings, the suggested unfolding hash function with factor four provides the most significant throughput of around 4196.30 Mbps. In contrast, the suggested unfolding with factor two surpassed the classic SHA-256 design in terms of maximum frequency. As a result, the throughput of SHA-256 increases 13.7% compared to unfolding factor two and 58.1% improvement from the conventional design of SHA-256 design.

Scenario-Aware Program Specialization for Timing Predictability

The successful application of static program analysis strongly depends on flow facts of a program such as loop bounds, control-flow constraints, and operating modes. This problem heavily affects the design of real-time systems, since static program analyses are a prerequisite to determine the timing behavior of a program. For example, this becomes obvious in worst-case execution time (WCET) analysis, which is often infeasible without user-annotated flow facts. Moreover, many timing simulation approaches use statically derived timings of partial program paths to reduce simulation overhead. Annotating flow facts on binary or source level is either error-prone and tedious, or requires specialized compilers that can transform source-level annotations along with the program during optimization. To overcome these obstacles, so-called scenarios can be used. Scenarios are a design-time methodology that describe a set of possible system parameters, such as image resolutions, operating modes, or application-dependent flow facts. The information described by a scenario is unknown in general but known and constant for a specific system. In this article, 1 we present a methodology for scenario-aware program specialization to improve timing predictability. Moreover, we provide an implementation of this methodology for embedded software written in C/C++. We show the effectiveness of our approach by evaluating its impact on WCET analysis using almost all of TACLeBench–achieving an average reduction of WCET of 31%. In addition, we provide a thorough qualitative and evaluation-based comparison to closely related work, as well as two case studies.

A Prototype Unit of a Distributed Sensor System for Ecological Monitoring

Introduction. In this article, the basic principles of ecological monitoring were considered, and the possibilities of constructing sensor systems were analysed. It was proposed to use the NB-IoT low-energy telecommunication standard as a basic wireless protocol for ecological system development, which ensures effective communication of network devices. A prototype of the system was constructed, and algorithms for receiving and transmitting signals were simulated.Aim. To construct a prototype of a transceiver based on the NB-IoT standard and perform its simulation. To utilize digital twin in MatLab to create the proposed system.Materials and methods. The prototype was constructed using the Xilinx Zedboard evaluation board and transceiver on AD9361 chip, and the simulation was performed using the MatLab 2010 software package.Results. The results of the simulation in the channel with the additive white Gaussian noise (AWGN) were obtained, and the level of the detected synchronization signals of the NB-IoT standard was determined. The receiver and transmitter of the NB-IoT standard were implemented on the Xilinx Zedboard evaluation board. The timing simulation results show that the designed system can be tested in a real environment. The power consumption and resource utilization of the constructed wireless sensor network prototype unit were determined. Conclusion. The results obtained via the simulation process show that the designed prototype of the communication system works correctly, and the produced signal meets all the requirements of the NB-IoT standard. The results can be used for creating a domestic manufactured, specialized integrated chip for data units of ecological monitoring systems.

Three-Stage Analysis of the Maximum Accommodation Capacity of a Distribution System with High Photovoltaic Penetration

The safety and stability of a distribution network will be affected by high photovoltaic (PV) penetration. Therefore, it is of great significance to evaluate the PV accommodation capacity of a distribution network and to select an appropriate PV accommodation scheme. This paper assesses the PV accommodation capacity of a distribution network with an improved algorithm and optimizes the accommodation scheme with a comprehensive index. First, the PSO (particle swarm optimization)–Monte Carlo algorithm is used to evaluate the maximum accommodation capacity of a distribution network with PV integration. Second, a year-round voltage timing simulation is performed to analyze the node voltage that exceeds the limit under the planned PV capacity, which is higher than the previously evaluated maximum accommodation capacity. Finally, the staged control strategy of the PV inverter and energy storage is carried out to select the scheme for the sizing and siting of energy storage. The simulation tests use a 10 kV standard distribution network as an example for PV evaluation and PV accommodation scheme selection to verify the feasibility and effectiveness of the proposed model.

Implementation of AMBA Based AHB2APB Bridge

The Advance Micro controller Bus Architecture bus protocol is used to build high performance SoC designs (system on chip). This achieves communication through the connection of different functional blocks ( or IP ). By using multiple controllers and peripherals, it makes possible to develop multiprocessor unit. It provides reusability of IP of different buses of AMBA, which can reduce the communication gap between high performance buses and low speed buses. To perform high-speed pipelined data transfers, AMBA based embedded system becomes a demanding hypothesis analytical wise, by using different bus signals supported by AMBA. To synthesize as well as simulate the composite annexation which connects advance high performance bus and advance peripheral bus which known as AHB2APB Bridge in addition to no data loss during transfer is the main target of this work. Implementation of bridge module is designed in Verilog HDL and functional and timing simulation of bridge module are done on a platform of Xilinx.

Vectored-Bloom Filter for IP Address Lookup: Algorithm and Hardware Architectures

The Internet Protocol (IP) address lookup is one of the most challenging tasks for Internet routers, since it requires to perform packet forwarding at wire-speed for tens of millions of incomming packets per second. Efficient IP address lookup algorithms have been widely studied to satisfy this requirement. Among them, Bloom filter-based approach is attractive in providing high performance. This paper proposes a high-speed and flexible architecture based on a vectored-Bloom filter (VBF), which is a space-efficient data structure that can be stored in a fast on-chip memory. An off-chip hash table is infrequently accessed, only when the VBF fails to provide address lookup results. The proposed architecture has been evaluated through both a behavior simulation with C language and a timing simulation with Verilog. The hardware implementation result shows that the proposed architecture can achieve the throughput of 5 million packets per second in a field programmable gate array (FPGA) operated at 100 MHz.

High-Resolution DPWM For DC-DC Buck Converter using Sigma-Delta Modulation Techniques

in this paper, a 13-bit hybrid DPWM structure which consists of a second-order Σ-∆ modulator having 6-bit resolution and a counter-comparator block with the 7-bit resolution is designed. The Σ-∆ modulator is based on error feedback concept which increases the effective resolution of DPWM by 6-bit and at the same time reduces clock power requirements and noise disturbances. The timing simulation waveforms of the designed DPWM architecture are verified and PWM pulses of the desirable duty cycle are generated. The Σ-Δ modulator based DPWM is used to drive the power MOSFETs of switching buck converter and Inductor current output voltage waveforms are observed. Ripple quantities of 17.5% and 0.07% are obtained for Inductor current and output voltage which are within the upper limits of 20% and 1% respectively. The steady value of the output voltage obtained is 0.99955V. The result obtained validates the Hybrid DPWM design.