scholarly journals Convolution Accelerator Designs Using Fast Algorithms

Algorithms ◽  
2019 ◽  
Vol 12 (5) ◽  
pp. 112 ◽  
Author(s):  
Yulin Zhao ◽  
Donghui Wang ◽  
Leiou Wang
Keyword(s):  
Power Consumption ◽  
Digital Signal Processor ◽  
Fast Algorithms ◽  
Digital Signal ◽  
Practical Implementation ◽  
Great Success ◽  
Field Programmable ◽  
Limited Power ◽  
And Performance ◽  
Logic Resource

Convolutional neural networks (CNNs) have achieved great success in image processing. However, the heavy computational burden it imposes makes it difficult for use in embedded applications that have limited power consumption and performance. Although there are many fast convolution algorithms that can reduce the computational complexity, they increase the difficulty of practical implementation. To overcome these difficulties, this paper proposes several convolution accelerator designs using fast algorithms. The designs are based on the field programmable gate array (FPGA) and display a better balance between the digital signal processor (DSP) and the logic resource, while also requiring lower power consumption. The implementation results show that the power consumption of the accelerator design based on the Strassen–Winograd algorithm is 21.3% less than that of conventional accelerators.

scholarly journals Argus CNN Accelerator Based on Kernel Clustering and Resource-Aware Pruning

2021 ◽  
Vol 27 (3) ◽  
pp. 57-70
Author(s):  
Damjan M. Rakanovic ◽  
Vuk Vranjkovic ◽  
Rastislav J. R. Struharik
Keyword(s):  
Digital Signal Processor ◽  
State Of The Art ◽  
Digital Signal ◽  
Pruning Algorithm ◽  
Kernel Clustering ◽  
Field Programmable ◽  
Comparable Performance ◽  
On Chip ◽  
Resource Characteristics ◽  
Resource Aware

Paper proposes a two-step Convolutional Neural Network (CNN) pruning algorithm and resource-efficient Field-programmable gate array (FPGA) CNN accelerator named “Argus”. The proposed CNN pruning algorithm first combines similar kernels into clusters, which are then pruned using the same regular pruning pattern. The pruning algorithm is carefully tailored for FPGAs, considering their resource characteristics. Regular sparsity results in high Multiply-accumulate (MAC) efficiency, reducing the amount of logic required to balance workloads among different MAC units. As a result, the Argus accelerator requires about 170 Look-up tables (LUTs) per Digital Signal Processor (DSP) block. This number is close to the average LUT/DPS ratio for various FPGA families, enabling balanced resource utilization when implementing Argus. Benchmarks conducted using Xilinx Zynq Ultrascale + Multi-Processor System-on-Chip (MPSoC) indicate that Argus is achieving up to 25 times higher frames per second than NullHop, 2 and 2.5 times higher than NEURAghe and Snowflake, respectively, and 2 times higher than NVDLA. Argus shows comparable performance to MIT’s Eyeriss v2 and Caffeine, requiring up to 3 times less memory bandwidth and utilizing 4 times fewer DSP blocks, respectively. Besides the absolute performance, Argus has at least 1.3 and 2 times better GOP/s/DSP and GOP/s/Block-RAM (BRAM) ratios, while being competitive in terms of GOP/s/LUT, compared to some of the state-of-the-art solutions.

An Improved Method Based on FPGA and DSP for Designing FBG Sensor Analyzer

2013 ◽  
Vol 760-762 ◽  
pp. 70-75
Author(s):  
Xiao Qing Luo ◽  
Rong Hu ◽  
Bing Hui Zheng
Keyword(s):  
Digital Signal Processor ◽  
Digital Signal ◽  
External Parameter ◽  
Wavelength Shift ◽  
Sensing Technology ◽  
Field Programmable ◽  
Signal Peak ◽  
Key Steps ◽  
Bragg Grating Sensor ◽  
Temperature Strain

Fiber Bragg sensors become research focus of sensing technology, and have been widely used in many applications. This paper proposed a novel Fiber Bragg Grating sensor analyzer based on FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) platform, which converted external parameter changes into wavelength shift in fiber Bragg gratings. The system can measure real-time temperature, strain, pressure, displacement and others through key steps including data acquisition, clutter Filtering, signal peak detection, Gaussian curve fitting and weighted wavelength calculation to carry out wavelength demodulation. Moreover, it is able to achieve fault diagnosis and positioning of the fiber link. Experimental results show that the system has advantages of low power consumption, good linearity, strong robustness, high precision and resolution on wavelength demodulation. And the system is still stable and reliable after a long test under different conditions.

Design and Performance Test of Digital Rebalance Loop for MEMS Gyroscope

2006 ◽  
Vol 326-328 ◽  
pp. 249-252 ◽  
Author(s):  
Byung Su Chang ◽  
Jang Gyu Lee ◽  
Tae Sam Kang
Keyword(s):  
Digital Signal Processor ◽  
Performance Test ◽  
Digital Signal ◽  
System Model ◽  
Digital Controller ◽  
Control Technique ◽  
Response Analysis ◽  
Frequency Response Analysis ◽  
Mems Gyroscope ◽  
And Performance

In this paper, a digital rebalance loop for MEMS gyroscope is designed and its performance test is performed. First, the system model of MEMS gyroscope is established by dynamic analysis. Then, the digital rebalance loop is designed using modern control technique. The performance of the digital rebalance loop is compared with that of conventional PID rebalance loop. Through frequency response analysis using MATLAB and experiments using a real MEMS gyroscope and digital controller, which is realized using digital signal processor (DSP), it is confirmed that the controller improves the performance of the gyroscope.

Design and Analysis of Piezoelectric Transducer Based Resonant Actuation Systems

Aerospace ◽  
2005 ◽  
Author(s):  
Jun-Sik Kim ◽  
K. W. Wang ◽  
Edward C. Smith
Keyword(s):  
Power Consumption ◽  
Digital Signal Processor ◽  
Digital Signal ◽  
Design Guidelines ◽  
Resonant Peak ◽  
Negative Effects ◽  
Actuation System ◽  
Dsp System ◽  
Resonant Systems ◽  
Mechanical Tuning

The objective of this research is to address some of the important design issues of the recently developed piezoelectric resonant actuation system (RAS) concept. The RAS is achieved through both mechanical and electrical tailoring. With mechanical tuning, the resonant frequencies of the actuation system (includes the piezoelectric actuator and the related mechanical and electrical elements for actuation) can be adjusted to the required actuation frequencies. This obviously will increase the authority of the actuation system. To further enhance controllability and robustness, the actuation resonant peak can be significantly broadened and flattened with electrical tailoring through the aid of an electric network of inductance, resistance, and negative capacitance. Therefore, one can achieve a high authority actuator without the negative effects of resonant systems. In this investigation, the RAS is analyzed and compared to an equivalent mechanical system to provide better physical understandings. Design guidelines of the RAS are derived in a dimensionless form, and the optimal values of the electrical components are explicitly determined. A method of implementing the actuator circuitry is proposed and realized via a digital signal processor (DSP) system. Performance of the resonant actuation system is analyzed and verified experimentally on a full-scale piezoelectric tube actuator for light class helicopter rotor control. The electric power consumption of the RAS is analyzed and discussed in terms of the power factor and apparent power. It is demonstrated that a piezoelectric resonant actuation system with proper tunings not only yields high authority with a broad frequency bandwidth but also is electrically efficient in terms of power consumption.

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