scholarly journals A Review of Self-Coherent Optical Transceivers: Fundamental Issues, Recent Advances, and Research Directions

2021 ◽  
Vol 11 (16) ◽  
pp. 7554
Author(s):  
Isiaka Alimi ◽  
Romil Patel ◽  
Nuno Silva ◽  
Chuanbowen Sun ◽  
Honglin Ji ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Dynamic Environment ◽  
Digital Signal ◽  
Research Directions ◽  
Recent Advances ◽  
Heterogeneous Nature ◽  
Signal Processing Algorithms ◽  
Processing Algorithms

This paper reviews recent progress on different high-speed optical short- and medium-reach transmission systems. Furthermore, a comprehensive tutorial on high-performance, low-cost, and advanced optical transceiver (TRx) paradigms is presented. In this context, recent advances in high-performance digital signal processing algorithms and innovative optoelectronic components are extensively discussed. Moreover, based on the growing increase in the dynamic environment and the heterogeneous nature of different applications and services to be supported by the systems, we discuss the reconfigurable and sliceable TRxs that can be employed. The associated technical challenges of various system algorithms are reviewed, and we proffer viable solutions to address them.

An Approach to Motion Control Applications Based on Advanced Programmable Devices

2012 ◽  
Vol 49 (3) ◽  
pp. 243-259 ◽  
Author(s):  
Juvenal Rodríguez-Reséndiz ◽  
Fortino Mendoza-Mondragón ◽  
Roberto A. Gómez-Loenzo ◽  
M. Agustín Martínez-Hernández ◽  
Victor H. Mucino
Keyword(s):  
Motion Control ◽  
Digital Signal Processor ◽  
High Speed ◽  
High Performance ◽  
Engineering Students ◽  
Low Cost ◽  
Digital Signal ◽  
Hybrid Architecture ◽  
Servo Drive ◽  
Control Applications

In this article a methodology for constructing a simple servo loop for motion control applications which is suitable for educational applications is presented. The entire hardware implementation is demonstrated, focusing on a microcontroller-based (μC) servo amplifier and a field programmable gate array-digital signal processor (FPGA-DSP) motion controller. A novel hybrid architecture-based digital stage is featured providing a low-cost servo drive and a high performance controller, which can be used as a basis for an industrial application. Communication between the computer and the controller is exploited in this project in order to perform a simultaneous adaptive servo tuning. The USB protocol has been put into operation in the user front-end because a high speed sampling frequency is required for the PC to acquire position feedback signals. A software interface is developed using educational software, enabling features not only limited to a motion profile but also the supervisory control and data acquisition (SCADA) topology of the system. A classical proportional-integral-derivative controller (PID) is programmed on a DSP in order to ensure a proper tracking of the reference at both low and high speeds in a d.c. motor. Furthermore, certain blocks are embedded on an FPGA. As a result, three of the most important technologies in signal processing are featured, permitting engineering students to understand several concepts covered in theoretical courses.

Novel Discrete Components Based Speed Controller for Induction Motor

2016 ◽  
Vol 7 (4) ◽  
pp. 1075
Author(s):  
Hussain Attia ◽  
Ali Sagafinia
Keyword(s):  
Induction Motor ◽  
Digital Signal Processor ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Digital Signal ◽  
Speed Control ◽  
Electronic System ◽  
Voltage Controlled Oscillator ◽  
Electronic Design

This paper presents an electronic design based on general purpose discrete components for speed control of a single phase induction motor drive. The MOSFETs inverter switching is controlled using Sampled Sinusoidal Pulse Width Modulation (SPWM) techniques with V/F method based on Voltage Controlled Oscillator (VCO). The load power is also controlled by a novel design to produce a suitable SPWM pulse. The proposed electronic system has ability to control the output frequency with flexible setting of lower limit to less than 1 Hz and to higher frequency limits to 55 Hz. Moreover, the proposed controller able to control the value of load voltage to frequency ratio, which plays a major parameter in the function of IM speed control. Furthermore, the designed system is characterized by easy manufacturing and maintenance, high speed response, low cost, and does not need to program steps as compared to other systems based on Microcontroller and digital signal processor (DSP) units. The complete proposed electronic design is made by the software of NI Multisim version 11.0 and all the internal sub-designs are shown in this paper. Simulation results show the effectiveness of electronic design for a promising of a high performance IM PWM drive.

scholarly journals Design of High-Speed Multiplier Architecture Based on Vedic Mathematics

2018 ◽  
Vol 7 (2.4) ◽  
pp. 105
Author(s):  
Chaitanya CVS ◽  
Sundaresan C ◽  
P R Venkateswaran ◽  
Keerthana Prasad ◽  
V Siva Ramakrishna
Keyword(s):  
High Speed ◽  
High Performance ◽  
Digital Signal ◽  
Expected Improvement ◽  
Trade Offs ◽  
Vlsi Technology ◽  
Essential Components ◽  
Signal Processing Algorithms ◽  
Computational Circuits ◽  
Almost All

High speed and efficient multipliers are essential components in today’s computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyamsutra of Vedic Multiplication has been presented in this paper. The multiplier architecture is implemented using Verilog coding and synthesise during Cadence RTL Compiler. Physical design is implemented using Cadence Encounter RTL-to-GDSII System using standard 180nm technology. The proposed multiplier architecture is compared with the conventional multiplier and the results show significant improvement in speed and power dissipation.

scholarly journals Low Complexity DSP for High Speed Optical Access Networking

2021 ◽  
Vol 11 (8) ◽  
pp. 3406
Author(s):  
Jinlong Wei ◽  
Cedric Lam ◽  
Ji Zhou ◽  
Ivan Aldaya ◽  
Elias Giacoumidis ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Noise Suppression ◽  
Low Cost ◽  
Optical Power ◽  
Digital Signal ◽  
Single Mode ◽  
Pulse Amplitude ◽  
Power Budget ◽  
Optical Access

A novel low-cost and energy-efficient approach for reaching 40 Gb/s signals is proposed for cost-sensitive optical access networks. Our proposed design is constituted of an innovative low-complex high-performance digital signal processing (DSP) architecture for pulse amplitude modulation (PAM-4), reuses existing commercial cost-effective 10-G components and eliminates the need of a power-hungry radio frequency (RF) component in the transmitter. Using a multi-functional 17-tap reconfigurable adaptive Volterra-based nonlinear equalizer with noise suppression, significant improvement in receiver optical power sensitivity is achieved. Results show that over 30 km of single-mode fiber (SMF) a link power budget of 33 dB is feasible at a bit-error-rate (BER) threshold of 10−3.

A Transputer Processing System Interface for The Evaluation of Digital Signal Processing Algorithms

1994 ◽  
Vol 31 (1) ◽  
pp. 54-65
Author(s):  
C. T. Pointon ◽  
R. A. Carrasco
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Low Cost ◽  
Processing System ◽  
Digital Signal ◽  
Computational Performance ◽  
System Input ◽  
Signal Processing Algorithms ◽  
Processing Algorithms ◽  
The Time Domain

A transputer processing system interface for the evaluation of digital signal processing algorithms The design and construction of a low-cost transputer processing system input/output (I/O) interface for the acquisition and retrieval of data, and its use in the evaluation of the computational performance characteristics of discrete convolution in the time domain, and fast convolution, using a non-look-up table fast Fourier transform (FFT) algorithm, is presented.

Introduction to Audio and Speech Signal Processing

2011 ◽  
pp. 1-20
Author(s):  
Hector Perez-Meana ◽  
Mariko Nakano-Miyatake
Keyword(s):  
Signal Processing ◽  
Hearing Aids ◽  
Speech Signal ◽  
High Performance ◽  
Digital Signal ◽  
Speech Signal Processing ◽  
Signal Processing Algorithms ◽  
Important Amount ◽  
Processing Algorithms ◽  
Signal Processors

The development of very efficient digital signal processors has allowed the implementation of high performance signal processing algorithms to solve an important amount of practical problems in several engineering fields, such as telecommunications, in which very efficient algorithms have been developed to storage, transmission, and interference reductions; in the audio field, where signal processing algorithms have been developed to enhancement, restoration, copy right protection of audio materials; in the medical field, where signal processing algorithms have been efficiently used to develop hearing aids systems and speech restoration systems for alaryngeal speech signals. This chapter presents an overview of some successful audio and speech signal processing algorithms, providing to the reader an overview of this important technology, some of which will be analyzed with more detail in the accompanying chapters of this book.

scholarly journals Non-Power-of-Two FFTs: Exploring the Flexibility of the Montium TP

2009 ◽  
Vol 2009 ◽  
pp. 1-12 ◽  
Author(s):  
Marcel D. van de Burgwal ◽  
Pascal T. Wolkotte ◽  
Gerard J. M. Smit
Keyword(s):  
High Performance ◽  
Processing Time ◽  
Digital Signal ◽  
Reconfigurable Architectures ◽  
Coarse Grain ◽  
Signal Processing Algorithms ◽  
Successful Approach ◽  
Processing Algorithms ◽  
Time Accuracy ◽  
High Performance Computation

Coarse-grain reconfigurable architectures, like the Montium TP, have proven to be a very successful approach for low-power and high-performance computation of regular digital signal processing algorithms. This paper presents the implementation of a class of non-power-of-two FFTs to discover the limitations and Flexibility of the Montium TP for less regular algorithms. A non-power-of-two FFT is less regular compared to a traditional power-of-two FFT. The results of the implementation show the processing time, accuracy, energy consumption and Flexibility of the implementation.

scholarly journals Towards a Glass New World: The Role of Ion-Exchange in Modern Technology

2021 ◽  
Vol 11 (10) ◽  
pp. 4610
Author(s):  
Simone Berneschi ◽  
Giancarlo C. Righini ◽  
Stefano Pelli
Keyword(s):  
Ion Exchange ◽  
Communication Networks ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Modern Technology ◽  
Historical Background ◽  
Wide Range ◽  
Happy Marriage

Glasses, in their different forms and compositions, have special properties that are not found in other materials. The combination of transparency and hardness at room temperature, combined with a suitable mechanical strength and excellent chemical durability, makes this material indispensable for many applications in different technological fields (as, for instance, the optical fibres which constitute the physical carrier for high-speed communication networks as well as the transducer for a wide range of high-performance sensors). For its part, ion-exchange from molten salts is a well-established, low-cost technology capable of modifying the chemical-physical properties of glass. The synergy between ion-exchange and glass has always been a happy marriage, from its ancient historical background for the realisation of wonderful artefacts, to the discovery of novel and fascinating solutions for modern technology (e.g., integrated optics). Getting inspiration from some hot topics related to the application context of this technique, the goal of this critical review is to show how ion-exchange in glass, far from being an obsolete process, can still have an important impact in everyday life, both at a merely commercial level as well as at that of frontier research.

scholarly journals A Compact UWB Indoor and Through-Wall Radar with Precise Ranging and Tracking

2012 ◽  
Vol 2012 ◽  
pp. 1-11 ◽  
Author(s):  
Yinan Yu ◽  
Jian Yang ◽  
Tomas McKelvey ◽  
Borys Stoew
Keyword(s):  
Signal Processing ◽  
Theoretical Analysis ◽  
Short Range ◽  
Indoor Environment ◽  
Low Cost ◽  
Moving Target ◽  
Radiation Characteristics ◽  
Uwb Radar ◽  
Signal Processing Algorithms ◽  
Processing Algorithms

Ultrawideband (UWB) technology has many advantages compared to its narrowband counterpart in many applications. We present a new compact low-cost UWB radar for indoor and through-wall scenario. The focus of the paper is on the development of the signal processing algorithms for ranging and tracking, taking into account the particular properties of the UWB CMOS transceiver and the radiation characteristics of the antennas. Theoretical analysis for the algorithms and their evaluations by measurements are presented in the paper. The ranging resolution of this UWB radar has achieved 1-2 mm RMS accuracy for a moving target in indoor environment over a short range, and Kalman tracking algorithm functions well for the through-wall detection.

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