scholarly journals Design and Performance Analysis of FIR Filter for VLSI Applications

2020 ◽  
Vol 9 (3) ◽  
pp. 530-533
Keyword(s):  
Digital Signal Processor ◽  
Digital Signal ◽  
Fir Filter ◽  
Basic Part ◽  
Booth Multiplier ◽  
Working Frequency ◽  
Area Unit ◽  
And Performance ◽  
Basic Blocks ◽  
Wide Assortment

The Primary essential basis for planning and realization of Digital signal processor is space improvement and decrease in power utilization. The basic part for arranging and acknowledgment of processor is the FIR Filter. This Filter contains three basic blocks that area unit Adder blocks, memory block and number blocks. The execution of this Filter is basically subjective by the wide assortment that is the moderate block out of all. In this paper, the Filter has been planned using two completely different multipliers particularly Array multiplier and Booth multiplier. An upgrade has been finished in each with respect to space and lag. Additionally, minimum power utilization and degradation concerning lag and working frequency of the booth multiplier maintain extremely appropriate for the planning of the FIR Filter for less voltage and less power VLSI operations.

Design and Performance Test of Digital Rebalance Loop for MEMS Gyroscope

2006 ◽  
Vol 326-328 ◽  
pp. 249-252 ◽  
Author(s):  
Byung Su Chang ◽  
Jang Gyu Lee ◽  
Tae Sam Kang
Keyword(s):  
Digital Signal Processor ◽  
Performance Test ◽  
Digital Signal ◽  
System Model ◽  
Digital Controller ◽  
Control Technique ◽  
Response Analysis ◽  
Frequency Response Analysis ◽  
Mems Gyroscope ◽  
And Performance

In this paper, a digital rebalance loop for MEMS gyroscope is designed and its performance test is performed. First, the system model of MEMS gyroscope is established by dynamic analysis. Then, the digital rebalance loop is designed using modern control technique. The performance of the digital rebalance loop is compared with that of conventional PID rebalance loop. Through frequency response analysis using MATLAB and experiments using a real MEMS gyroscope and digital controller, which is realized using digital signal processor (DSP), it is confirmed that the controller improves the performance of the gyroscope.

scholarly journals Convolution Accelerator Designs Using Fast Algorithms

Algorithms ◽  
2019 ◽  
Vol 12 (5) ◽  
pp. 112 ◽  
Author(s):  
Yulin Zhao ◽  
Donghui Wang ◽  
Leiou Wang
Keyword(s):  
Power Consumption ◽  
Digital Signal Processor ◽  
Fast Algorithms ◽  
Digital Signal ◽  
Practical Implementation ◽  
Great Success ◽  
Field Programmable ◽  
Limited Power ◽  
And Performance ◽  
Logic Resource

Convolutional neural networks (CNNs) have achieved great success in image processing. However, the heavy computational burden it imposes makes it difficult for use in embedded applications that have limited power consumption and performance. Although there are many fast convolution algorithms that can reduce the computational complexity, they increase the difficulty of practical implementation. To overcome these difficulties, this paper proposes several convolution accelerator designs using fast algorithms. The designs are based on the field programmable gate array (FPGA) and display a better balance between the digital signal processor (DSP) and the logic resource, while also requiring lower power consumption. The implementation results show that the power consumption of the accelerator design based on the Strassen–Winograd algorithm is 21.3% less than that of conventional accelerators.

Real-Time Implementation of a Robust H∞ Controller for a 2-DOF Magnetic Micro-Levitation Positioner

1995 ◽  
Vol 117 (4) ◽  
pp. 637-640 ◽  
Author(s):  
Abdelfatah M. Mohamed ◽  
Bard Vestgaard ◽  
Ilene Busch-Vishniac
Keyword(s):  
Real Time ◽  
Robust Stability ◽  
Digital Signal Processor ◽  
Transfer Functions ◽  
Standard Form ◽  
Digital Signal ◽  
Performance Goals ◽  
Interactive Computing ◽  
Experimental Implementation ◽  
And Performance

Robust H∞ optimal control theory has proven to be one of the best techniques in linear control system design. The achievable robust stability and performance are high, but the resulting controllers are very complex and difficult to implement. As a result, few practical implementations of H∞ control can be found in the literature. This paper presents a robust H∞ controller for a two-degree-of-freedom magnetic micro-levitation positioner and its real time experimental implementation. The experimental device used in this study is designed for use in semiconductor manufacturing and consists of two U-shaped electromagnets and a manipulator. First, we describe the system dynamics in state space form. Second, the system which is unstable in nature is stabilized using the H∞ synthesis. The H∞ control design problem is described and formulated in the standard form with emphasis on the selection of weighting transfer functions that reflect robustness and performance goals. The interactive computing environment MATLAB is used to calculate the controller. Third, the controller is implemented digitally using a digital signal processor with 16 bit A/D and 12 bit D/A converters. Finally, some simulation and experimental results are presented. The results obtained show that robust stability against model uncertainties is achieved and the performance goals are satisfied.

Highly Integrated Radar Sensor-on-Chip

Frequenz ◽  
2012 ◽  
Vol 66 (5-6) ◽  
Author(s):  
Ralph Mende
Keyword(s):  
Radio Frequency ◽  
System Design ◽  
Integrated Circuit ◽  
Digital Signal Processor ◽  
Silicon Germanium ◽  
Digital Signal ◽  
Radar System ◽  
Radar Sensor ◽  
Shift Keying ◽  
And Performance

AbstractA highly integrated 24 GHz radar sensor is presented, based on a Radio Frequency Integrated Circuit (RFIC) which was specifically developed for a Frequency Modulated Shift Keying (FMSK) based Radar system design. Antenna, waveform, the Radio Frequency (RF) and Digital Signal Processor (DSP) module, the software design, cost and performance aspects will be described. The significant technical and economical advantages of the implemented Silicon-Germanium (SiGe) Bipolar CMOS (BiCMOS) transceiver are demonstrated. Some automotive and other applications based on this technology and new radar system design will be explained.

Digital Signal Processor: Architecture and Performance

1981 ◽  
Vol 60 (7) ◽  
pp. 1449-1462 ◽  
Author(s):  
J. R. Boddie ◽  
G. T. Daryanani ◽  
I. I. Eldumiati ◽  
R. N. Gadenz ◽  
J. S. Thompson ◽  
...  
Keyword(s):  
Digital Signal Processor ◽  
Digital Signal ◽  
Processor Architecture ◽  
And Performance ◽  
Signal Processor

scholarly journals DSP Prototype of a Chaos-Based Multi-User Communication System: Design and Performance Analysis

2006 ◽  
Vol 2 (2) ◽  
pp. 71
Author(s):  
Ljiljana Simic ◽  
Stevan Berber
Keyword(s):  
Digital Signal Processor ◽  
Communication System ◽  
Additive White Gaussian Noise ◽  
Digital Signal ◽  
System Capacity ◽  
Modulation Scheme ◽  
Chaotic Signals ◽  
Communication System Design ◽  
And Performance ◽  
Code Division Multiple

This paper presents the implementation of a multi-user chaos-based communication system in DSP (digital signal processor) technology. The system is based on the chaotic phase shift keying (CPSK) digital modulation scheme, where chaotic signals are used as the spreading sequences of a CDMA (code division multiple access) system. Using chaotic signals offers the advantages of increased security and higher system capacity compared with conventional sequences. The aim of this hardware implementation was to enable a comparison against analytical performance results for CPSK. The transceiver prototype was implemented on a 32-bit floating-point TigerSHARC DSP. Its bit error rate (BER) characteristics were measured in the presence of additive white Gaussian noise. The prototype achieves excellent BER performance, matching that of theoretical CPSK. The effects of the limited number precision of the hardware platform are thus negligible. However, due to the limited concurrency of DSP, the multi-user system only supports low data rates. Despite this, the prototype demonstrates that the CPSK scheme is a promising and viable CDMA option for the future.

Yield Enhancement Study: Process Variation and Design Margins Leading to Timing Issues in the RAM

2000 ◽  
Author(s):  
Srikanth Perungulam ◽  
Scott Wills ◽  
Greg Mekras
Keyword(s):  
Cross Sections ◽  
Digital Signal Processor ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Digital Signal ◽  
Yield Enhancement ◽  
Final Conclusion ◽  
Stage Separation ◽  
Study Process

Abstract This paper illustrates a yield enhancement effort on a Digital Signal Processor (DSP) where random columns in the Static Random Access Memory (SRAM) were found to be failing. In this SRAM circuit, sense amps are designed with a two-stage separation and latch sequence. In the failing devices the bit line and bit_bar line were not separated far enough in voltage before latching got triggered. The design team determined that the sense amp was being turned on too quickly. The final conclusion was that a marginal sense amp design, combined with process deviations, would result in this type of failure. The possible process issues were narrowed to variations of via resistances on the bit and bit_bar lines. Scanning Electron Microscope (SEM) inspection of the the Focused Ion Beam (FIB) cross sections followed by Transmission Electron Microscopy (TEM) showed the presence of contaminants at the bottom of the vias causing resistance variations.

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