scholarly journals Implementation of GA with Position Based Crossover-PX Technique for Size Optimization of BDD Mapped Adder Circuits

2020 ◽  
Vol 9 (3) ◽  
pp. 4215-4218
Keyword(s):  
Genetic Algorithm ◽  
Digital Circuits ◽  
Full Adder ◽  
System Optimization ◽  
Size Optimization ◽  
Variable Order ◽  
Decision Diagrams ◽  
Order Method ◽  
Binary Decision ◽  
Solution Formation

Binary Decision Diagrams or BDD are data structure used to represent single and multi-output digital circuits. BDD mapped adder circuits are used to represent different adder functions in a digital system. Optimization of adder circuits are done by optimizing the corresponding BDDs. In this work the optimization of BDD Mapped adder circuits are proposed by using genetic algorithm with position-based crossover-PX technique. The main feature of position-based crossover technique is that it is suitable for order-based solution formation. We compared our result with other existing variable order method available in BDD manipulation tool BuDDy-2.4. The result is obtained for Full Adder circuits of 1 to 8-bit size. Experimental results show the improvement of the proposed work over other techniques. The result is quite significant for large circuits i.e. full adder circuit having larger bit size.

scholarly journals Genetic algorithm for binary and functional decision diagrams optimization

2018 ◽  
Vol 31 (2) ◽  
pp. 169-187
Author(s):  
Stojkovic Suzana ◽  
Velickovic Darko ◽  
Moraga Claudio
Keyword(s):  
Genetic Algorithm ◽  
Genetic Algorithms ◽  
Data Structure ◽  
Optimization Problems ◽  
Binary Decision Diagrams ◽  
Size Optimization ◽  
Decision Diagrams ◽  
Crossover Operator ◽  
Binary Decision ◽  
Discrete Functions

Decision diagrams (DD) are a widely used data structure for discrete functions representation. The major problem in DD-based applications is the DD size minimization (reduction of the number of nodes), because their size is dependent on the variables order. Genetic algorithms are often used in different optimization problems including the DD size optimization. In this paper, we apply the genetic algorithm to minimize the size of both Binary Decision Diagrams (BDDs) and Functional Decision Diagrams (FDDs). In both cases, in the proposed algorithm, a Bottom-Up Partially Matched Crossover (BU-PMX) is used as the crossover operator. In the case of BDDs, mutation is done in the standard way by variables exchanging. In the case of FDDs, the mutation by changing the polarity of variables is additionally used. Experimental results of optimization of the BDDs and FDDs of the set of benchmark functions are also presented.

scholarly journals Synthesis of parallel adders from if-decision diagrams

2020 ◽  
pp. 61-70
Author(s):  
A. A. Prihozhy
Keyword(s):  
Time Complexity ◽  
Digital Circuits ◽  
Binary Decision Diagrams ◽  
Space Exploration ◽  
Decision Diagrams ◽  
Binary Decision ◽  
Longest Paths

Addition is one of the timing critical operations in most of modern processing units. For decades, extensive research has been done devoted to designing higher speed and less complex adder architectures, and to developing advanced adder implementation technologies. Decision diagrams are a promising approach to the efficient many-bit adder design. Since traditional binary decision diagrams does not match perfectly with the task of modelling adder architectures, other types of diagram were proposed. If-decision diagrams provide a parallel many-bit adder model with the time complexity of Ο(log2n) and area complexity of Ο(n×log2n). The paper propose a technique, which produces adder diagrams with such properties by systematically cutting the diagram’s longest paths. The if-diagram based adders are competitive to the known efficient Brent-Kung adder and its numerous modifications. We propose a blocked structure of the parallel if-diagram-based adders, and introduce an adder table representation, which is capable of systematic producing if-diagram of any bit-width. The representation supports an efficient mapping of the adder diagrams to VHDL-modules at structural and dataflow levels. The paper also shows how to perform the adder space exploration depending on the circuit fan-out. FPGA-based synthesis results and case-study comparisons of the if-diagram-based adders to the Brent-Kung and majority-invertor gate adders show that the new adder architecture leads to faster and smaller digital circuits.

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