Design of a Low-Voltage Low-Power CMOS Operational Amplifier

2013 ◽  
Vol 380-384 ◽  
pp. 3283-3286
Author(s):  
Lin Hai Cui ◽  
Rui Xu ◽  
Zhan Peng Jiang ◽  
Chang Chun Dong
Keyword(s):  
Low Power ◽  
Operational Amplifier ◽  
High Efficiency ◽  
Low Voltage ◽  
Low Frequency ◽  
Open Loop ◽  
Common Source ◽  
Output Stage ◽  
Input Stage ◽  
Current Mirrors

A low voltage, low power two-stage operational amplifier (op-amp) was proposed in this paper. A folded-cascode structure is used in the input stage of the amplifier to get high gain. Current mirrors are used in the input stage to make the transconduotance constant. A simple push-pull common source amplifier is adopted as the output stage to take the advantages of its high efficiency. The experimental results show that the unity-gain bandwidth is 12.5MHz, the low-frequency open-loop voltage gain is 100dB,the phase margin is 65°, and power dissipation is 98.8μw.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Design of a Low-Power Rail-to-Rail CMOS Operational Amplifier

2013 ◽  
Vol 380-384 ◽  
pp. 3304-3307
Author(s):  
Yang Guang ◽  
Bin Yu ◽  
Huang Hai
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Operational Amplifier ◽  
Circuit Simulation ◽  
Open Loop ◽  
Cmos Process ◽  
Output Stage ◽  
Class Ab ◽  
Op Amp ◽  
Rail To Rail

In this paper, an operational amplifier with low-power consumption has been designed. Using the complementary differential pair for the input stage and the class AB structure for the output stage, the common-mode input range and output swing of the proposed circuit could achieved rail-to-rail. Based on TSMC 0.18μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that the proposed op-amp has more than 100dB open loop gain, meanwhile the static power consumption is less than 300μw. The circuit's phase margin is 68 degrees, CMRR is 135dB and power supply rejection ratio is 63dB.

scholarly journals A 4-μW 0.8-V Rail-to-Rail Input/Output CMOS Fully Differential OpAmp

1970 ◽  
pp. 22
Author(s):  
M.R. Valero ◽  
S. Celma ◽  
N. Medrano
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Cmos Technology ◽  
Open Loop ◽  
Threshold Region ◽  
Input Output ◽  
Output Stage ◽  
Common Mode ◽  
Ultra Low Power ◽  
Rail To Rail

This paper presents an ultra low power rail-to-rail input/output operational amplifier (OpAmp) designed in a low cost 0.18 μm CMOS technology. In this OpAmp, rail-to-rail input operation is enabled by using complementary input pairs with gm control. To maximize the output swing a rail-to-rail output stage is employed. For low-voltage low-power operation, the operating transistors in the input and output stage are biased in the sub-threshold region. The simulated DC open loop gain is 51 dB, and the slew-rate is 0.04 V/μs with a 10 pF capacitive load connected to each of the amplifier outputs. For the same load, the simulated unity gain frequency is 131 kHz with a 64º phase margin. A common-mode feed-forward circuit (CMFF) increases CMRR, reducing drastically the variations in the output common mode voltage and keeping the DC gain almost constant. In fact, their relative error remains below 1.2 % for a (-20ºC, +120ºC) temperature span. In addition, the proposed OpAmp is very simple and consumes only 4 μW at 0.8 V supply.

Low Voltage, Low Power Gm-C Filter for Low Frequency Applications

2018 ◽  
Vol 14 (2) ◽  
pp. 266-274 ◽  
Author(s):  
G. Hanumantha Rao ◽  
S. Rekha
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Low Frequency

scholarly journals Low Power AVLS-TSPC based 2/3 Pre-Scaler

2019 ◽  
Vol 9 (1) ◽  
pp. 6687-6693
Keyword(s):  
Low Power ◽  
High Efficiency ◽  
Supply Voltage ◽  
Low Frequency ◽  
Cmos Technology ◽  
Frequency Signal ◽  
High Frequency Signal ◽  
Power Requirement ◽  
Fast Pace ◽  
Integer Division

The technology has grown at an ultra-fast pace along with the world. Small devices with less power and high efficiency are in demand. As the circuit size gets smaller, the power requirement increases due to a greater number of transistors. A pre-scaler is a circuit which reduces the high frequency signal to a low frequency signal by integer division. A new approach to low power pre-scaler is proposed in this paper, which is an add-on to the conventional pre-scaler circuit. A true single-phase clock (TSPC) circuit reduces the skew problems in the clock and is used to realize latches and flip-flops. The objective of low power is fulfilled by incorporating the Adaptive Voltage Level Source (AVLS) to TSPC based circuit. The proposed AVLS-TSPC based pre-scaler was analyzed for a frequency of 10 MHz with a supply voltage of 1.8 V for both divide by 2 and 3 modes. The proposed pre-scaler consumes considerably lesser power when compared to that of the existing pre-scaler circuit. The circuits are implemented in 180 nm CMOS technology using Cadence Virtuoso and simulated using Cadence Spectre.

Development of a 300°C capable SiC based operational amplifier

2010 ◽  
Vol 2010 (HITEC) ◽  
pp. 000305-000309 ◽  
Author(s):  
Vinayak Tilak ◽  
Cheng-Po Chen ◽  
Peter Losee ◽  
Emad Andarawis ◽  
Zachary Stum
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Operational Amplifier ◽  
Room Temperature ◽  
Open Loop ◽  
Common Source ◽  
Loop Gain ◽  
Long Term Stability ◽  
Silicon Silicon

Silicon carbide based ICs have the potential to operate at temperatures exceeding that of conventional semiconductors such as silicon. Silicon carbide (SiC) based MOSFETs and ICs were fabricated and measured at room temperature and 300°C. A common source amplifier was fabricated and tested at room temperature and high temperature. The gain at room temperature and high temperature was 7.6 and 6.8 respectively. A SiC MOSFET based operational amplifier was also fabricated and tested at room temperature and 300°C. The small signal open loop gain at 1kHz was 60 dB at room temperature and 57 dB at 300°C. Long term stability testing at 300°C of the MOSFET and common source amplifiers showed very little drift.

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