Application of PEM and OBIRCH to Defect Localization of Integrated Circuits

2014 ◽  
Vol 904 ◽  
pp. 277-281
Author(s):  
Jian Wen Lian ◽  
Xiao Ling Lin ◽  
Ruo He Yao
Keyword(s):  
Integrated Circuits ◽  
Failure Mechanisms ◽  
Photon Emission ◽  
Fault Isolation ◽  
Resistance Change ◽  
Microelectronic Devices ◽  
Application Condition ◽  
Defect Localization ◽  
Metal Interconnects ◽  
Fault Characterization

With the increasing integration and complexity of microelectronic devices, fault isolation has been challenged. Photon Emission Microscopy (PEM) and Optical Beam Induced Resistance Change (OBIRCH) are effective tools for defect localization and fault characterization in failure analysis. In this paper, the principles and different application condition of PEM and OBIRCH are discussed. PEM is very helpful for locating defects emitting photon, but can not detect the defects which have no photon emitting, such as shorted metal interconnects; OBIRCH as a complementary, has a high success rate for locating resistance defects. Two cases with failure mechanisms illuminated are presented to show the different application of PEM and OBIRCH.

Fault Isolation of Open Defects Using Space Domain Reflectometry

2012 ◽  
Author(s):  
Mayue Xie ◽  
Zhiguo Qian ◽  
Mario Pacheco ◽  
Zhiyong Wang ◽  
Rajen Dias ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Fault Isolation ◽  
Nondestructive Technique ◽  
Space Domain ◽  
New Approach ◽  
Defect Localization ◽  
Open Faults ◽  
Open Defects ◽  
Application Optimization ◽  
Rf Magnetic Field

Abstract Recently, a new approach for isolation of open faults in integrated circuits (ICs) was developed. It is based on mapping the radio-frequency (RF) magnetic field produced by the defective part fed with RF probing current, giving the name to Space Domain Reflectometry (SDR). SDR is a non-contact and nondestructive technique to localize open defects in package substrates, interconnections and semiconductor devices. It provides 2D failure isolation capability with defect localization resolution down to 50 microns. It is also capable of scanning long traces in Si. This paper describes the principles of the SDR and its application for the localization of open and high resistance defects. It then discusses some analysis methods for application optimization, and gives examples of test samples as well as case studies from actual failures.

scholarly journals Preliminary Study on the Model of Thermal Laser Stimulation for Defect Localization in Integrated Circuits

2020 ◽  
Vol 10 (23) ◽  
pp. 8576
Author(s):  
Han Yang ◽  
Rui Chen ◽  
Jianwei Han ◽  
Yanan Liang ◽  
Yingqi Ma ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Induced Resistance ◽  
Seebeck Effect ◽  
Comprehensive Model ◽  
Induced Voltage ◽  
Efficient Technology ◽  
Resistance Change ◽  
Scanning Velocity ◽  
Laser Stimulation ◽  
Defect Localization

Thermal Laser Stimulation (TLS) is an efficient technology for integrated circuit defect localization in Failure Analysis (FA) laboratories. It contains Optical Beam-Induced Resistance Change (OBIRCH), Thermally-Induced Voltage Alteration (TIVA), and Seebeck Effect Imaging (SEI). These techniques respectively use the principle of laser-induced resistance change and the Seebeck effect. In this paper, a comprehensive model of TLS technology is proposed. Firstly, the model presents an analytical expression of the temperature variation in Integrated Circuits (IC) after laser irradiation, which quantificationally shows the positive correlation with laser power and the negative correlation with scanning velocity. Secondly, the model describes the opposite influence of laser-induced resistance change and the Seebeck effect in the device. Finally, the relationship between the current variation measured in the experiment and other parameters, especially the voltage bias, is well explained by the model. The comprehensive model provides theoretical guidance for the efficient and accurate defect localization of TLS technology.

Application of Advanced Back-Side Optical Techniques in ASICs

2013 ◽  
Vol 21 (3) ◽  
pp. 30-35
Author(s):  
Douglas Martin ◽  
Samuel Beilin ◽  
Brett Hamilton ◽  
Darin York ◽  
Philip Baker ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Photon Emission ◽  
Back Side ◽  
Voltage Imaging ◽  
Root Cause ◽  
Silicon Transistors ◽  
Cause Of Failure ◽  
Metal Interconnects ◽  
Application Specific

Failure analysis is important in determining root cause for appropriate corrective action. In order to perform failure analysis of microelectronic application-specific integrated circuits (ASICs) delidding the device is often required. However, determining root cause from the front side is not always possible due to shadowing effects caused by the ASIC metal interconnects. Therefore, back-side polishing is used to reveal an unobstructed view of the ASIC silicon transistors. This paper details how back-side polishing in conjunction with laser-scanned imaging (LSI), laser voltage imaging (LVI), laser voltage probing (LVP), photon emission microscopy (PEM), and laser-assisted device alterations (LADA) were used to uncover the root cause of failure of two ASICs.

Backside Deprocessing of CMOS SOI Devices for Physical Defect and Failure Analysis

2003 ◽  
Author(s):  
Seth J. Prejean ◽  
Joseph Shannon
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Flip Chip ◽  
Fault Isolation ◽  
Oxide Semiconductor ◽  
Easy Access ◽  
Induced Voltage ◽  
Emission Analysis ◽  
Defect Localization ◽  
Soi Devices

Abstract This paper describes improvements in backside deprocessing of CMOS (Complimentary Metal Oxide Semiconductor) SOI (Silicon On Insulator) integrated circuits. The deprocessing techniques described here have been adapted from a previous research publication on backside deprocessing of bulk CMOS integrated circuits [1]. The focus of these improvements was to provide a repeatable and reliable methodology of deprocessing CMOS devices from the backside. We describe a repeatable and efficient technique to deprocess flip chip packaged devices and unpackaged die from the backside. While this technique has been demonstrated on SOI and bulk devices, this paper will focus on the latest SOI technology. The technique is useful for quick and easy access to the transistor level while preserving the metal interconnects for further analysis. It is also useful for deprocessing already thinned or polished die without removing them from the package. Removing a thin die from a package is very difficult and could potentially damage the device. This is especially beneficial when performing physical failure analysis of samples that have been back thinned for the purpose of fault isolation and defect localization techniques such as: LIVA (Laser Induced Voltage Alteration), TIVA (Thermally Induce Voltage Alteration), SDL [2] (Soft Defect Localization), and TRE (Time Resolved Emission) analysis. An important fundamental advantage of deprocessing SOI devices is that the BOX (Buried Oxide) layer acts as a chemical etch stop when etching the backside or bulk silicon. This leaves the transistor active silicon intact for analysis. Further delayering allows for the inspection of the active silicon, gate oxide, silicide, spacers, and poly. After deprocessing the transistor level, the metal layers are still intact and, in most cases, still electrically connected to the outside world. This can provide additional failure analysis opportunities.

From IDDQ Fault Detection to Defect Localization in Logic CMOS Integrated Circuits: Key Issues

1999 ◽  
Author(s):  
Philippe Perdu ◽  
Romain Desplats
Keyword(s):  
Fault Detection ◽  
Integrated Circuits ◽  
Test Pattern ◽  
Pattern Generation ◽  
Fault Isolation ◽  
Iddq Testing ◽  
Accurate Localization ◽  
Contactless Testing ◽  
Defect Localization ◽  
Key Issues

Abstract IDDQ testing detects a majority of faults in logic ICs. To improve defect coverage with very short test patterns, IDDQ testing has been integrated in fault simulators embedded with automatic test pattern generation (ATPG) algorithms. Nevertheless, for failure analysis purposes, this progress has not eliminated the complex task of fault isolation at the silicon level of ICs. Defect localization is facilitated with IDDQ testing because the defect is detected as soon as it is activated inside the device. At the failed vector, abnormal IDDQ current is measured and accurate localization of the corresponding defect inside the chip can be performed. Thermally related techniques or emission microscopy can be used for this localization process. Very powerful tools like electron beam testers can also be used to deeply analyze faulty devices by internal contactless testing. In this paper, we will present an application of IDDQ testing for fault detection and some key issues regarding localization of the corresponding defect: • Appropriate techniques, • Switching from electrical testing to fault localization, • Modifying the test pattern to shorten the localization process, • Constructing a localization method based on an IDDQ diagnostic.

Failure Analysis of Sub-Micron Semiconductor Integrated Circuit Using Backside Photon Emission Microscopy

1999 ◽  
Author(s):  
Soon Lim ◽  
Jian Hua Bi ◽  
Lian Choo Goh ◽  
Soh Ping Neo ◽  
Sudhindra Tatti
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Photon Emission ◽  
Fault Isolation ◽  
Integrated Circuit Fabrication ◽  
Circuit Fabrication ◽  
Emission Microscopy ◽  
On Chip

Abstract The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.

3-D Defect Localization by Measurement and Modeling of the Dynamics of Heat Transport in Deep Sub-Micron Devices

2007 ◽  
Author(s):  
A. Reverdy ◽  
M. de la Bardonnie ◽  
L.F.Tz. Kwakman ◽  
M. Lamy ◽  
C. Wyon ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Success Rate ◽  
Heat Transport ◽  
Fault Isolation ◽  
Isolation Method ◽  
Signal Phase ◽  
Resistance Change ◽  
Time Constants ◽  
Measurement Results ◽  
Defect Localization

Abstract Due to relentless down scaling of device geometries, failure analysis is getting more and more complex. As a matter of fact, the success rate of Thermal Laser Stimulation (TLS) techniques drops significantly for 90/65 nm CMOS devices because of the lack of x, y and z accuracy. In our aim to improve the TLS based fault isolation method, we have studied thermal time-constant signatures using a Modulated Optical Beam Induced Resistance Change (MOBIRCH) technique that may provide accurate x and y submicron resolution as well as depth or z-information of defects in the interconnection part of devices. Both Modeling and measurement results indicate that OBIRCH signal phase shifts and heat-up & cool-down time constants indeed do correlate with the location, dimensions and density of the structures studied.

Low Temperature Fault Isolation Using Soft Defect Localization

2012 ◽  
Author(s):  
Kristopher D. Staller
Keyword(s):  
Low Temperatures ◽  
Laser Scanning ◽  
Low Cost ◽  
Fault Isolation ◽  
Laser Scanning Microscopy ◽  
Cold Temperature ◽  
Multiple Point ◽  
Defect Localization ◽  
Low Levels

Abstract Cold temperature failures are often difficult to resolve, especially those at extreme low levels (< -40°C). Momentary application of chill spray can confirm the failure mode, but is impractical during photoemission microscopy (PEM), laser scanning microscopy (LSM), and multiple point microprobing. This paper will examine relatively low-cost cold temperature systems that can hold samples at steady state extreme low temperatures and describe a case study where a cold temperature stage was combined with LSM soft defect localization (SDL) to rapidly identify the cause of a complex cold temperature failure mechanism.

Laser Failure Isolation Techniques Demonstrated On Test Structures

2008 ◽  
Author(s):  
Frank S. Arnold
Keyword(s):  
Integrated Circuits ◽  
Laser Beam ◽  
Case Studies ◽  
Induced Resistance ◽  
Simple Test ◽  
Resistance Change ◽  
Cross Sectional ◽  
Beam Focusing ◽  
Isolation Techniques ◽  
Heating Effects

Abstract To be better prepared to use laser based failure isolation techniques on field failures of complex integrated circuits, simple test structures without any failures can be used to study Optical Beam Induced Resistance Change (OBIRCH) results. In this article, four case studies are presented on the following test structures: metal strap, contact string, VIA string, and comb test structure. Several experiments were done to investigate why an OBIRCH image was seen in certain areas of a VIA string and not in others. One experiment showed the OBRICH variation was not related to the cooling and heating effects of the topology, or laser beam focusing. A 4 point probe resistance measurement and cross-sectional views correlated with the OBIRCH results and proved OBIRCH was able to detect a variation in VIA fabrication.

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