A Comparison of High Temperature Performance of SiC DMOSFETs and JFETs

2007 ◽  
Vol 556-557 ◽  
pp. 775-778 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Sumi Krishnaswami ◽  
Brett A. Hull ◽  
Bradley Heath ◽  
Fatima Husna ◽  
...  
Keyword(s):  
High Temperature ◽  
Inversion Layer ◽  
Interface State ◽  
State Density ◽  
Temperature Dependent ◽  
Temperature Application ◽  
Layer Resistance ◽  
Flow Through ◽  
Pn Junctions ◽  
Very High

High temperature characteristics of 4H-SiC power JFETs and DMOSFETs are presented in this paper. Both devices are based on pn junctions in 4H-SiC, and are capable of 300oC operation. The 4H-SiC JFET showed very predictable, well understood temperature dependent characteristics, because the current conduction depends on the drift of electrons in the bulk region, which is not restricted by traps in the MOS interface or at the pn junctions. On the other hand, in a 4H-SiC DMOSFET, electrons must flow through the MOS inversion layer with a very high interface state density. At high temperatures, the transconductance of the device improves and threshold voltage shifts negative because less electrons are trapped in the interface states, resulting in a much lower MOS channel resistance. This cancels out the increase in drift layer resistance, and as a result, a temperature insensitive on-resistance can be demonstrated. The performance of the two devices are compared, and a discussion of issues for their high temperature application is presented.

Study of the impact of interface traps associated with SiNX passivation on AlGaN/GaN MIS-HEMTs

2022 ◽  
Author(s):  
Rijo Baby ◽  
Anirudh Venugopalrao ◽  
Hareesh Chandrasekar ◽  
Srinivasan Raghavan ◽  
Muralidharan Rangrajan ◽  
...  
Keyword(s):  
High Temperature ◽  
Gate Dielectric ◽  
Drain Current ◽  
Interface State ◽  
Interface States ◽  
State Density ◽  
Temperature Dependent ◽  
The Impact ◽  
Surface Conduction ◽  
Magnitude Improvement

Abstract In this work, we show that a bilayer SiNx passivation scheme which includes a high-temperature annealed SiNx as gate dielectric, significantly improves both ON and OFF state performance of AlGaN/GaN MISHEMTs. From devices with different SiNx passivation schemes, surface and bulk leakage paths were determined. Temperature-dependent MESA leakage studies showed that the surface conduction could be explained using a 2-D variable range hopping mechanism along with the mid-gap interface states at the GaN(cap)/ SiNx interface generated due to the Ga-Ga metal like bonding states. It was found that the high temperature annealed SiNx gate dielectric exhibited the lowest interface state density and a two-step C-V indicative of a superior quality SiNx/GaN interface as confirmed from conductance and capacitance measurements. High-temperature annealing helps in the formation of Ga-N bonding states, thus reducing the shallow metal-like interface states. MISHEMT measurements showed a significant reduction in gate leakage and a 4-orders of magnitude improvement in the ON/OFF ratio while increasing the saturation drain current (IDS) by a factor of 2. Besides, MISHEMTs with 2-step SiNx passivation exhibited a relatively flat transconductance profile, indicative of lower interface states density. The dynamic Ron with gate and drain stressing measurements also showed about 3x improvements in devices with bilayer SiNx passivation.

Oxide Traps Probed by Transient Capacitance Measurements on Lateral SiO2/4H-SiC MOSFETs

2018 ◽  
Vol 924 ◽  
pp. 285-288 ◽  
Author(s):  
Patrick Fiorenza ◽  
Ferdinando Iucolano ◽  
Mario Saggio ◽  
Fabrizio Roccaforte
Keyword(s):  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Interface Traps ◽  
Temperature Dependent ◽  
Discharge Time ◽  
Capacitance Measurements ◽  
Gate Capacitance ◽  
Transient Capacitance ◽  
Oxide Traps

In this paper, near interface traps (NITs) in lateral 4H-SiC MOSFETs were investigated employing temperature dependent transient gate capacitance measurements (C-t). TheC-tmeasurements as a function of temperature indicated that the effective NITs discharge time is temperature independent and electrons from NITs are emitted toward the semiconductor via-tunnelling and/or trap-to-trap tunnelling. The NITs discharge time was modelled taking into account also the interface state density in a distributed circuit and it allowed to locate traps within a distance of about 1.3nm from the SiO2/4H-SiC interface.

Effect of Thermal Stability and Roughness on Electrical Properties of Tantalum Oxide Gates

1999 ◽  
Vol 567 ◽  
Author(s):  
G.B. Alers ◽  
L.A. Stirling ◽  
R.B. Vandover ◽  
J.P. Chang ◽  
D.J. Werder ◽  
...  
Keyword(s):  
High Temperature ◽  
Gate Dielectrics ◽  
Tantalum Oxide ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
Effective Dielectric Constant ◽  
Leakage Currents ◽  
Temperature Plasma ◽  
The Impact

ABSTRACTGate dielectrics with an effective SiO2 thickness of 1.6 nm (100 Hz) have been fabricated using chemical vapor deposition of tantalum oxide directly on silicon. A low temperature plasma anneal process was used to passivate excess traps in the oxide layer and to avoid degradation of capacitance and leakage after high temperature processing. Stable capacitance-voltage characteristics were obtained after the plasma anneal with an interface state density of ∼ 1012 cm−2 before post metallization anneal. We have examined the impact of high temperature processes and crystallization on the roughness for 10nm – 50nm films of Ta2O5 films on Si and SiN. The impact of roughness on capacitance and leakage current is examined through calculations assuming a Gaussian distribution of thickness across the capacitor with two conductive contacts. It is found that when the rms roughness exceeds about 20% of the film thickness then an increase in capacitance is observed that can be mistaken as an effective dielectric constant increase. The increase in capacitance due to roughness is accompanied by an exponential increase in leakage currents that ultimately degrades the charge storage capacity of the oxide.

scholarly journals Reduction of interface state density in SiC (0001) MOS structures by post-oxidation Ar annealing at high temperature

AIP Advances ◽  
2017 ◽  
Vol 7 (4) ◽  
pp. 045008 ◽  
Author(s):  
Takuma Kobayashi ◽  
Jun Suda ◽  
Tsunenobu Kimoto
Keyword(s):  
High Temperature ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Mos Structures

Modelling of the Anomalous Field-Effect Mobility Peak of O-Ta2Si/4H-SiC High-k MOSFETs Measured in Strong Inversion

2006 ◽  
Vol 527-529 ◽  
pp. 1059-1062
Author(s):  
Amador Pérez-Tomás ◽  
Miquel Vellvehi ◽  
Narcis Mestres ◽  
José Millan ◽  
P. Vennegues ◽  
...  
Keyword(s):  
Field Effect ◽  
Inversion Layer ◽  
Interface State ◽  
State Density ◽  
Gate Insulator ◽  
Coulomb Scattering ◽  
Field Effect Mobility ◽  
Tunnel Current ◽  
High K ◽  
Strong Inversion

A high field-effect mobility peak (50 cm2/Vs) has been extracted in (0001) Si face 4HSiC MOSFETs with oxidized Ta2Si (O-Ta2Si) high-k dielectric (k~20) as gate insulator, with their gates in the strong inversion regime. The interface state density (Dit) has not been particularly reduced in O-Ta2Si capacitors. This anomalous mobility enhancement is explained in terms of Coulomb scattering reduction and quantified using a physical model based on the Lombardi mobility model. The anomalous mobility increase is closely related to the leakage current, and also to the gate breakdown mechanism. We propose a model for which the observed interfacial SiO2 tunnel current combined with Poole-Frenkel mechanisms at the O-Ta2Si gate generates a sufficiently low abrupt transition in gate breakdown to obtain an effective passivation of the interface traps. Under these conditions, the increase of free carriers in the inversion layer induced by the gate leakage diminishes the effect of the interface trap Coulomb scattering.

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