Study of the impact of interface traps associated with SiNX passivation on AlGaN/GaN MIS-HEMTs

2022 ◽  
Author(s):  
Rijo Baby ◽  
Anirudh Venugopalrao ◽  
Hareesh Chandrasekar ◽  
Srinivasan Raghavan ◽  
Muralidharan Rangrajan ◽  
...  
Keyword(s):  
High Temperature ◽  
Gate Dielectric ◽  
Drain Current ◽  
Interface State ◽  
Interface States ◽  
State Density ◽  
Temperature Dependent ◽  
The Impact ◽  
Surface Conduction ◽  
Magnitude Improvement

Abstract In this work, we show that a bilayer SiNx passivation scheme which includes a high-temperature annealed SiNx as gate dielectric, significantly improves both ON and OFF state performance of AlGaN/GaN MISHEMTs. From devices with different SiNx passivation schemes, surface and bulk leakage paths were determined. Temperature-dependent MESA leakage studies showed that the surface conduction could be explained using a 2-D variable range hopping mechanism along with the mid-gap interface states at the GaN(cap)/ SiNx interface generated due to the Ga-Ga metal like bonding states. It was found that the high temperature annealed SiNx gate dielectric exhibited the lowest interface state density and a two-step C-V indicative of a superior quality SiNx/GaN interface as confirmed from conductance and capacitance measurements. High-temperature annealing helps in the formation of Ga-N bonding states, thus reducing the shallow metal-like interface states. MISHEMT measurements showed a significant reduction in gate leakage and a 4-orders of magnitude improvement in the ON/OFF ratio while increasing the saturation drain current (IDS) by a factor of 2. Besides, MISHEMTs with 2-step SiNx passivation exhibited a relatively flat transconductance profile, indicative of lower interface states density. The dynamic Ron with gate and drain stressing measurements also showed about 3x improvements in devices with bilayer SiNx passivation.

scholarly journals Demonstration of AlGaN/GaN MISHEMT on Si with Low-Temperature Epitaxy Grown AlN Dielectric Gate

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1858
Author(s):  
Matthew Whiteside ◽  
Subramaniam Arulkumaran ◽  
Yilmaz Dikme ◽  
Abhinay Sandupatla ◽  
Geok Ing Ng
Keyword(s):  
Low Temperature ◽  
Gate Dielectric ◽  
Drain Current ◽  
High Electron Mobility Transistors ◽  
Interface State ◽  
State Density ◽  
High Electron ◽  
Gate Leakage ◽  
Annealing Effects ◽  
Low Temperature Epitaxy

AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMT) with a low-temperature epitaxy (LTE)-grown single crystalline AlN gate dielectric were demonstrated for the first time and the post-gate annealing effects at 400 °C were studied. The as-deposited LTE-AlN MISHEMT showed a maximum drain current (IDmax) of 708 mA/mm at a gate bias of 4 V and a maximum extrinsic transconductance (gmmax) of 129 mS/mm. The 400 °C annealed MISHEMT exhibited an increase of 15% in gmmax, an order of magnitude reduction in reverse gate leakage and about a 3% suppression of drain current (ID) collapse. The increase of gmmax by post-gate annealing is consistent with the increase of 2DEG mobility. The suppression of ID collapse and the reduction of gate leakage current is attributed to the reduction of interface state density (5.0 × 1011 cm−2eV−1) between the AlN/GaN interface after post-gate annealing at 400 °C. This study demonstrates that LTE grown AlN is a promising alternate material as gate dielectric for GaN-based MISHEMT application.

scholarly journals Fully Ion Implanted Normally-Off GaN DMOSFETs with ALD-Al2O3 Gate Dielectrics

Materials ◽  
2019 ◽  
Vol 12 (5) ◽  
pp. 689 ◽  
Author(s):  
Michitaka Yoshino ◽  
Yuto Ando ◽  
Manato Deki ◽  
Toru Toyabe ◽  
Kazuo Kuriyama ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Drain Current ◽  
Atomic Layer ◽  
Surface Concentration ◽  
Interface State ◽  
State Density ◽  
Free Standing ◽  
Al2o3 Gate Dielectric ◽  
P Type ◽  
Ion Implanted

A normally-off GaN double-implanted vertical MOSFET (DMOSFET) with an atomic layer deposition (ALD)-Al2O3 gate dielectric film on a free-standing GaN substrate fabricated by triple ion implantation is presented. The DMOSFET was formed with Si ion implanted source regions in a Mg ion implanted p-type base with N ion implanted termination regions. A maximum drain current of 115 mA/mm, maximum transconductance of 19 mS/mm at a drain voltage of 15 V, and a threshold voltage of 3.6 V were obtained for the fabricated DMOSFET with a gate length of 0.4 μm with an estimated p-type base Mg surface concentration of 5 × 1018 cm−3. The difference between calculated and measured Vths could be due to the activation ratio of ion-implanted Mg as well as Fermi level pinning and the interface state density. On-resistance of 9.3 mΩ·cm2 estimated from the linear region was also attained. Blocking voltage at off-state was 213 V. The fully ion implanted GaN DMOSFET is a promising candidate for future high-voltage and high-power applications.

Effect of Thermal Stability and Roughness on Electrical Properties of Tantalum Oxide Gates

1999 ◽  
Vol 567 ◽  
Author(s):  
G.B. Alers ◽  
L.A. Stirling ◽  
R.B. Vandover ◽  
J.P. Chang ◽  
D.J. Werder ◽  
...  
Keyword(s):  
High Temperature ◽  
Gate Dielectrics ◽  
Tantalum Oxide ◽  
Chemical Vapor ◽  
Interface State ◽  
State Density ◽  
Effective Dielectric Constant ◽  
Leakage Currents ◽  
Temperature Plasma ◽  
The Impact

ABSTRACTGate dielectrics with an effective SiO2 thickness of 1.6 nm (100 Hz) have been fabricated using chemical vapor deposition of tantalum oxide directly on silicon. A low temperature plasma anneal process was used to passivate excess traps in the oxide layer and to avoid degradation of capacitance and leakage after high temperature processing. Stable capacitance-voltage characteristics were obtained after the plasma anneal with an interface state density of ∼ 1012 cm−2 before post metallization anneal. We have examined the impact of high temperature processes and crystallization on the roughness for 10nm – 50nm films of Ta2O5 films on Si and SiN. The impact of roughness on capacitance and leakage current is examined through calculations assuming a Gaussian distribution of thickness across the capacitor with two conductive contacts. It is found that when the rms roughness exceeds about 20% of the film thickness then an increase in capacitance is observed that can be mistaken as an effective dielectric constant increase. The increase in capacitance due to roughness is accompanied by an exponential increase in leakage currents that ultimately degrades the charge storage capacity of the oxide.

Subthreshold Characteristics and Interface State Density of a-Si:H TFT

1993 ◽  
Vol 297 ◽  
Author(s):  
Keiji Maeda ◽  
Hiroki Koyanagi ◽  
Toshihide Jinnai
Keyword(s):  
Gate Voltage ◽  
Room Temperature ◽  
Drain Current ◽  
Interface State ◽  
Interface States ◽  
State Density ◽  
Subthreshold Region ◽  
Layer Width ◽  
Capacitance Measurements ◽  
Voltage Swing

Inverted-staggered a-Si:H TFT was prepared by successive PECVD of a- SiN1.7:H and a- Si:H layers. Drain current ID vs gate voltage VG characteristics of the TFT were investigated. The gate-voltage swing defined by S=dVG/d(log ID) in the subthreshold region was 1.4 V at room temperature. If the observed S value is attributed to the bulk gap state density, the space- charge layer width is estimated to be about 450 A. This value is too small compared with the a-Si:H layer width of about 3000 A in the TFT, which exhibits good performance. On the other hand, if the S value is attributed to the interface states, a state density of 1.5×l012 (cm2 eV)-1 is necessary. Nearly the same density, (l-2)xl012 (cm2 eV)-1, nearly independent of the energy level, was obtained in oura-SiN1.7:H/c-Si interface by capacitance measurements. Therefore, it is concluded that the interface states are the main origin of the subthreshold characteristics in our a-Si:H TFT.

Advances in GaAs Mosfet's Using Ga2O3(Gd2O3) as Gate Oxide

1999 ◽  
Vol 573 ◽  
Author(s):  
Y. C. Wang ◽  
M. Hong ◽  
J. M. Kuo ◽  
J. P. Mannaerts ◽  
J. Kwo ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Drain Current ◽  
Interface State ◽  
State Density ◽  
Inversion Mode ◽  
Order Of Magnitude ◽  
Novel Processing ◽  
Reported Data ◽  
Processing Techniques ◽  
Current Drift

ABSTRACTIn this article, we review the recent progress on GaAs MOSFET's using in-situ MBE-grown Ga2O3(Gd2O3) as the gate dielectric. Both depletion-mode (D-mode) and inversion-mode (I-mode) GaAs MOSFET's with negligible drain current drift and hysteresis are demostrated. The absence of drain current drift and hysteresis indicates that the excellent stability of the oxide and low oxide/GaAs interface state density have been achieved. The drain current density and transconductance are about one order of magnitude higher than the best previous reported data in the literature for an inversion-mode GaAs MOSFET. Excellent high frequency and power performances were also measured from the depletion-mode devices. These improvements are attributed to the excellent Ga2O3(Ga2O3) oxide properties and novel processing techniques.

Temperature-Dependent Current-Voltage Characteristics in ZnO Based Schottky Diodes

2014 ◽  
Vol 894 ◽  
pp. 391-395
Author(s):  
Hog Young Kim ◽  
Ahrum Sohn ◽  
Dong Wook Kim
Keyword(s):  
Schottky Diodes ◽  
Interface State ◽  
State Density ◽  
Current Transport ◽  
Temperature Dependent ◽  
Conduction Path ◽  
Current Voltage ◽  
Different Temperatures ◽  
Increasing Temperature ◽  
Surface Conduction

Using currentvoltage (IV) measurements, the temperature-dependent current transport in Ag/Zn-polar ZnO Schottky diodes was investigated. Both the series and shunt resistances of the diode were altered at the different temperatures, which were related to the amount of free carriers and the formation of a vacuum-activated surface conduction path, respectively. The reverse biased current transport was associated with a thermally assisted tunneling field emission of carriers and the Poole-Frenkel effect, for higher and lower voltages, respectively. The average interface state density decreased with increasing temperature, which was due to a result of molecular restructuring and reordering and/or variation of the ideality factor with temperatures across the Ag/ZnO interface.

A Comparison of High Temperature Performance of SiC DMOSFETs and JFETs

2007 ◽  
Vol 556-557 ◽  
pp. 775-778 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Sumi Krishnaswami ◽  
Brett A. Hull ◽  
Bradley Heath ◽  
Fatima Husna ◽  
...  
Keyword(s):  
High Temperature ◽  
Inversion Layer ◽  
Interface State ◽  
State Density ◽  
Temperature Dependent ◽  
Temperature Application ◽  
Layer Resistance ◽  
Flow Through ◽  
Pn Junctions ◽  
Very High

High temperature characteristics of 4H-SiC power JFETs and DMOSFETs are presented in this paper. Both devices are based on pn junctions in 4H-SiC, and are capable of 300oC operation. The 4H-SiC JFET showed very predictable, well understood temperature dependent characteristics, because the current conduction depends on the drift of electrons in the bulk region, which is not restricted by traps in the MOS interface or at the pn junctions. On the other hand, in a 4H-SiC DMOSFET, electrons must flow through the MOS inversion layer with a very high interface state density. At high temperatures, the transconductance of the device improves and threshold voltage shifts negative because less electrons are trapped in the interface states, resulting in a much lower MOS channel resistance. This cancels out the increase in drift layer resistance, and as a result, a temperature insensitive on-resistance can be demonstrated. The performance of the two devices are compared, and a discussion of issues for their high temperature application is presented.

Impact of Interfacial Nitridation of HfO2 High-k Gate Dielectric Stack on 4H-SiC

2007 ◽  
Vol 996 ◽  
Author(s):  
Rajat Mahapatra ◽  
Amit K. Chakraborty ◽  
Peter Tappin ◽  
Bing Miao ◽  
Alton B. Horsfall ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Gate Dielectric ◽  
Interface State ◽  
State Density ◽  
Breakdown Field ◽  
Electrical Measurements ◽  
Electrical Stress ◽  
High K ◽  
Pile Up ◽  
Current Characteristics

AbstractHfO2 films were grown on SiO2/4H-SiC and SiON/4H-SiC layers by evaporation of metallic Hf in an electron beam deposition system followed by thermal oxidation. X-ray photoelectron spectroscopy confirmed the formation of HfO2 films. There is no evidence of formation of hafnium silicide or carbon pile up at the surface as well as at the interfacial layer. Electrical measurements show the presence of fewer slow traps in the HfO2/SiON gate dielectric stack on 4H-SiC and comparable values of interface state density. The HfO2/SiON stack layer improves leakage current characteristics with a higher breakdown field and has better reliability under electrical stress.

Low- and High-Frequency C–V Characteristics of Au/n-GaN/n-GaAs

2018 ◽  
Vol 18 (06) ◽  
pp. 1850039
Author(s):  
Abderrezzaq Ziane ◽  
Mohamed Amrani ◽  
Abdelaziz Rabehi ◽  
Zineb Benamara
Keyword(s):  
Schottky Diode ◽  
High Frequency ◽  
High Vacuum ◽  
Low Frequency ◽  
Interface State ◽  
Interface States ◽  
State Density ◽  
Ultra High Vacuum ◽  
Active Nitrogen ◽  
Capacitance Voltage

Au/GaN/GaAs Schottky diode created by the nitridation of n-GaAs substrate which was exposed to a flow of active nitrogen created by a discharge source with high voltage in ultra-high vacuum with two different thicknesses of GaN layers (0.7[Formula: see text]nm and 2.2[Formula: see text]nm), the I–V and capacitance–voltage (C–V) characteristics of the Au/n-GaN/n-GaAs structures were studied for low- and high-frequency at room temperature. The measurements of I–V of the Au/n-GaN/n-GaAs Schottky diode were found to be strongly dependent on bias voltage and nitridation process. The electrical parameters are bound by the thickness of the GaN layer. The capacitance curves depict a behavior indicating the presence of interface state density, especially in the low frequency. The interface states density was calculated using the high- and low-frequency capacitance curves and it has been shown that the interface states density decreases with increasing of nitridation of the GaAs.

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