Underfill Design for Low-k Dielectrics and Lead Free Applications
As technology nodes progress to 32/28nm and beyond underfill materials are presented with the significantly challenging task of maintaining bump protection while ensuring ultra low-K dielectric (ULK/ELK) integrity. This challenge is further complicated by the trend toward RoHS compliancy(lead-free) and a ever increasing die size. Through extensive research and testing, several specifically formulated underfill materials were determined acceptable solutions for these complex issues. As technology nodes progress to smaller process generations a high stress concentration is seen at the dielectric layer during thermal cycling. This stress is a typical result of a high glass transition temperature (Tg) / high strength material that often leads to a cracking failure mode of the thin dielectric layer. Too low of a Tg presents a high stress concentration on the bumps which once again constitutes failure, this time however the crack is typically seen at the bump location. This high stress concentration seen at the bumps is more significant when lead free bumps are considered due to their inherent fragile nature. Underfill materials must now be specifically formulated and optimized to solve these failure modes for a large variable of package types. This paper will discuss solutions to typical failure modes currently seen with reliability testing of present and future technologies.