Wafer Level Package for MEMS with TSVs and Hermetic Seal

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002314-002335
Author(s):  
Akinori Shiraishi ◽  
Mitsutoshi Higashi ◽  
Kei Murayama ◽  
Yuichi Taguchi ◽  
Kenichi Mori
Keyword(s):  
Silicon Wafer ◽  
Adhesive Bonding ◽  
Anodic Bonding ◽  
Back Side ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Mems Device ◽  
Bonding Method ◽  
Wafer Level Package

In recent years, downsizing of MEMS package and high accuracy MEMS device mounting have been strongly required from expanding applications that using MEMS not only for industrial and automobile but also for consumer typified mobile phone. In order to achieve that, it is appropriate to use Silicon package that can be mounted at wafer level packaging. Silicon package is made of monocrystal silicon wafer. The deep cavity is fabricated on monocrystal silicon wafer by Wet or Dry etching. And MEMS device can be mounted on the cavity. The electrical connecting between front side and back side of cavity portion is achieved by TSVs that located on the bottom of cavity. Hermetic seal can be achieved by using glass or silicon wafer bonding method. By using a driver device wafer (before dicing) as the cap for hermetic seal, smaller size and smaller number of parts module can be fabricated. In this report, methods and designs for hermetic seal with wafer level process were examined. Methods that applied were polyimide adhesive bonding, anodic bonding and Au-In solder bonding. Location of TSVs on the bottom of cavity and thickness of diaphragm with TSVs was also examined. Silicon package for piezo type gyro MEMS that designed by the result of evaluation was fabricated. This package used optimized Au-In solder bonding for hermetic seal and optimized location of TSVs for interconnection. That was designed over 50% thinner than conventional ceramic packages. Characteristics of hermetic seal were evaluated by Q factor of gyro MEMS that mounted inside of the silicon package. It is confirmed that performance of sealing are good enough for running of the MEMS.

Wafer Level Micropackaging of MEMS Devices Using Thin Film Anodic Bonding

2002 ◽  
Vol 729 ◽  
Author(s):  
Lauren E. S. Rohwer ◽  
Andrew D. Oliver ◽  
Melissa V. Collins
Keyword(s):  
Shear Strength ◽  
Test Sample ◽  
Anodic Bonding ◽  
Mems Devices ◽  
Wafer Level ◽  
Thermal Actuators ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Leak Testing ◽  
Before And After

AbstractA wafer level packaging technique that involves anodic bonding of Pyrex wafers to released surface micromachined wafers is demonstrated. Besides providing a hermetic seal, this technique allows full wafer release, provides protection during die separation, and offers the possibility of integration with optoelectronic devices. Anodic bonding was performed under applied voltages up to 1000 V, and temperatures ranging from 280 to 400°C under vacuum (10-4Torr). The quality of the bonded interfaces was evaluated using shear strength testing and leak testing. The shear strength of Pyrex-to-polysilicon and aluminum bonds was ∼10-15 MPa. The functionality of surface micromachined polysilicon devices was tested before and after anodic bonding. 100% of thermal actuators, 94% of torsional ratcheting actuators, and 70% of microengines functioned after bonding. The 70% yield was calculated from a test sample of 25 devices.

Shorting out bonding method for multi-stack anodic bonding and its application in wafer-level packaging

2020 ◽  
Vol 34 (32) ◽  
pp. 2050369
Author(s):  
Yifang Liu ◽  
Tingting Dai ◽  
Peiqin Xie ◽  
Lingyun Wang ◽  
Zhan Zhan ◽  
...  
Keyword(s):  
Anodic Bonding ◽  
Wafer Level ◽  
Temperature Property ◽  
Mems Packaging ◽  
Long Term Stability ◽  
Wafer Level Packaging ◽  
Voltage Division ◽  
Rc Circuit ◽  
Bonding Method

Silicon/glass anodic bonding is widely investigated during MEMS packaging of multi-stack structures. The electrical behavior of anode bonding can be described as the charging and discharging process of RC circuit. Here, we conduct the equivalent RC circuit model analysis and experimental investigation, and demonstrate that voltage division and electricity leakage are the dilemma for the conventional multi-stack anodic bonding. By using feedthrough, the feasibility and convenience of “shorting out bonding” is presented, which is exampled through the wafer-level packaging of the MEMS gyroscope. Result from the sensor’s vacuum characterization reveals that shorting out bonding for multi-stack silicon/glass structures is an effective method for wafer-level packaging due to long-term stability and low temperature property.‘

Parametric Design and Reliability Analysis of WIT Wafer Level Packaging

2000 ◽  
Author(s):  
Y. T. Lin ◽  
P. J. Tang ◽  
K. N. Chiang
Keyword(s):  
Reliability Analysis ◽  
Flip Chip ◽  
Parametric Design ◽  
Material Selection ◽  
New Technology ◽  
Rapid Expansion ◽  
Wafer Level ◽  
Good Reliability ◽  
Wafer Level Packaging ◽  
Wafer Level Package

Abstract The demands of electronic packages toward lower profile, lighter weight, and higher density of I/O lead to rapid expansion in the field of flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent needs of high I/O density and good reliability characteristic lead to the evolution of the ultra high-density type of non-solder interconnection such as the wire interconnect technology (WIT). The new technology using copper posts to replace the solder bumps as interconnections shown a great improvement in the reliability life. Moreover, this type of wafer level package could achieve higher I/O density, as well as ultra fine pitch. This research will focus on the reliability analysis of the WIT package structures in material selection and structural design, etc. This research will use finite element method to analyze the physical behavior of packaging structures under thermal cycling condition to compare the reliability characteristics of conventional wafer level package and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature dependent material properties will be applied to all of the models.

scholarly journals Wafer Level Packaging Technology Applied to Pixel Detectors

2021 ◽  
Vol 9 ◽  
Author(s):  
Paolo Conci ◽  
Giovanni Darbo ◽  
Andrea Gaudiello ◽  
Claudia Gemme ◽  
Stefano Girardi ◽  
...  
Keyword(s):  
High Energy Physics ◽  
High Energy ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Technical Requirements ◽  
Pixel Detectors ◽  
Single Sensor ◽  
Wafer Processing ◽  
Wafer Level Package ◽  
Energy Physics

Pixel technology is commonly used in the tracking systems of High Energy Physics detectors with physical areas that have largely increased in the last decades. To ease the production of several square meters of sensitive area, the possibility of using the industrial Wafer Level Packaging to reassemble good single sensor tiles from multiple wafers into a reconstructed full wafer is investigated. This process reconstructs wafers by compression molding using silicon charged epoxy resin. We tested high glass transition temperature low-stress epoxy resins filled with silica particles to best match the thermal expansion of the silicon die. These resins are developed and characterized for industrial processes, designed specifically for fan-out wafer-level package and panel-level packaging. In order to be compatible with wafer processing during the hybridization of the pixel detectors, such as the bump-bonding, the reconstructed wafer must respect challenging technical requirements. Wafer planarity, tile positioning accuracy, and overall thickness are amongst the main ones. In this paper the description of the process is given and preliminary results on a few reconstructed wafers using dummy tiles are reported. Strategies for Wafer Level Packaging improvements are discussed together with future applications to 3D sensors or CMOS pixel detectors.

Fabrication of Glass Mixing Channels and Silicon Detection Cell with 45˚ Mirror Surfaces for the Indophenol Sensing Device

2005 ◽  
Vol 475-479 ◽  
pp. 1849-1852
Author(s):  
Kyu Shik Shin ◽  
Joon Shik Park ◽  
Kwang Bum Park ◽  
Hyo Derk Park ◽  
Jeong Rim Kim ◽  
...  
Keyword(s):  
Silicon Wafer ◽  
Tetramethylammonium Hydroxide ◽  
The Other ◽  
Anodic Bonding ◽  
Glass Wafer ◽  
Island Size ◽  
Hene Laser ◽  
Propyl Alcohol ◽  
Detection Cell ◽  
Bonding Method

Design and fabrication of micro mixing cells and detection cells were investigated. Glass micro mixing cells with island structures among channels were fabricated using sand blaster methods. Depth and width of mixing channel were 200 ㎛ and 180 ㎛ and island size was 90 ㎛ by 90 ㎛. Two 45° mirrors surfaces faced on each other in one detection cell which were fabricated by silicon anisotropic etching using 20% TMAH (Tetramethylammonium hydroxide) solution with 20% or 30% IPA (iso propyl alcohol) at 80°C, respectively. Up side glass wafer for mixing cell and down side silicon wafer for detection cell were bonded using anodic bonding method at 350ı, -600 V and 300 N. Synthetic indophenol was injected at inlet and moved to the detection cell through the mixing channel. HeNe laser of 632.8 nm was focused on one side of a 45° mirror, and passed through indophenol solution until the other side of a 45° mirror. The light of 632.8 nm was absorbed in indophenol solution between two 45° mirrors at detection cell. By the Beer-Lambert’s law, indophenol concentration could be calculated from the measured result of the absorbance.

Residual Stress in Silicon Caused by Cu-Sn Wafer-Level Packaging

2013 ◽  
Author(s):  
Maaike M. V. Taklo ◽  
Astrid-Sofie Vardøy ◽  
Ingrid De Wolf ◽  
Veerle Simons ◽  
H. J. van de Wiel ◽  
...  
Keyword(s):  
Residual Stress ◽  
Integrated Circuit ◽  
High Performance ◽  
White Light Interferometry ◽  
Wafer Level ◽  
Noticeable Effect ◽  
Micro Raman Spectroscopy ◽  
Wafer Level Packaging ◽  
Mems Device ◽  
Specific Technology

The level of stress in silicon as a result of applying Cu-Sn SLID wafer level bonding to hermetically encapsulate a high-performance infrared bolometer device was studied. Transistors are present in the read out integrated circuit (ROIC) of the device and some are located below the bond frame. Test vehicles were assembled using Cu-Sn SLID bonding and micro-Raman spectroscopy was applied on cross sectioned samples to measure stress in the silicon near the bond frame. The test vehicles contained cavities and the bulging of the structures was studied using white light interferometry. The test vehicles were thermally stressed to study possible effects of the treatments on the level of stress in the silicon. Finite element modeling was performed to support the understanding of the various observations. The measurements indicated levels of stress in the silicon that can affect transistors in regions up to 15 μm below the bond frame. The observed levels of stress corresponded well with the performed modeling. However, no noticeable effect was found for the ROIC used in this work. The specific technology used for the fabrication of the ROIC of a MEMS device is thus decisive. The level of stress did not appear to change as a result of the imposed thermal stress. The level of stress caused by the bond frame can be expected to stay constant throughout the lifetime of a device.

Damascene-Patterned Metal-Adhesive (Cu-BCB) Redistribution Layers

2006 ◽  
Vol 970 ◽  
Author(s):  
Ronald J. Gutmann ◽  
J. Jay McMahon ◽  
Jian-Qiang Lu
Keyword(s):  
Bonding Strength ◽  
Adhesive Bonding ◽  
Process Integration ◽  
Three Dimensional ◽  
Adhesive Layer ◽  
Wafer Level ◽  
Technology Platform ◽  
Metal Bonding ◽  
Wafer Level Packaging ◽  
Metal Metal

ABSTRACTA monolithic, wafer-level three-dimensional (3D) technology platform is described that is compatible with next-generation wafer level packaging (WLP) processes. The platform combines the advantages of both (1) high bonding strength and adaptability to IC wafer topography variations with spin-on dielectric adhesive bonding and (2) process integration and via-area advantages of metal-metal bonding. A copper-benzocyclobutene (Cu-BCB) process is described that incorporates single-level damascene-patterned Cu vias with partially-cured BCB as the bonding adhesive layer. A demonstration vehicle consisting of a two-wafer stack of 2-4 μm diameter vias has shown the bondability of both Cu-to-Cu and BCB-to-BCB. Planarization conditions to achieve BCB-BCB bonding with low-resistance Cu-Cu contacts have been examined, with wafer-scale planarization requirements compared to other 3D platforms. Concerns about stress induced at the tantalum (Ta) liner-to-BCB interface resulting in partial delamination are discussed. While across-wafer uniformity has not been demonstrated, the viability of this WLP-compatible 3D platform has been shown.

Low Cost Metal Mini-Cap Process for Suspended MEMS Device Packaging

2005 ◽  
Author(s):  
Wei Chung ◽  
Leonardo Wang ◽  
W. Fang
Keyword(s):  
Low Cost ◽  
Selective Etching ◽  
Mems Devices ◽  
Wafer Level ◽  
Carrier Wafer ◽  
Mems Device ◽  
Die Bonding ◽  
To Come ◽  
Wafer Level Package

A new wafer capping process is investigated in this study. The objective of this study is to come out a simple and low cost wafer capping process to make the capped MEMS device wafers “transparent” to traditional IC assembly processes. The carrier wafers with metal mini-caps are bonded on the MEMS device wafers through solder bonding, and the mini-caps are then transferred and left on the MEMS device wafer through a selective etching of the carrier wafers. The metal mini-cap capped device wafers are virtually of the same thickness as original ones; in addition, the transferred metal mini-caps provide a mechanical protection to the MEMS devices during the consequent assembly processes such as wafer dicing, die bonding, molding, etc. With an additional design of 2nd level interconnection on the mini-cap carrier wafer, the transferred MEMS device wafers can be singulated and become a wafer level package with compliant leads.

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