Nanometer-thin pure boron CVD layers as material barrier to Au or Cu metallization of Si

Metallization layers of aluminum, gold, or copper are shown to be protected from interactions with silicon substrates by thin boron layers grown by chemical-vapor deposition (CVD) at 450 °C. A 3-nm-thick B-layer was studied in detail. It formed the p+-anode region of PureB diodes that have a metallurgic junction depth of zero on n-type Si. The metals were deposited by electron-beam-assisted physical vapor deposition (EBPVD) at room temperature and annealed at temperatures up to 500 °C. In all cases, the B-layer was an effective material barrier between the metal and Si, as verified by practically unchanged PureB diode I–V characteristics and microscopy inspections of the deposited layers. For this result, it was required that the Si surface be clean before B-deposition. Any Si surface contamination was otherwise seen to impede a complete B-coverage giving, sometimes Schottky-like, current increases. For Au, room-temperature interactions with the Si through such pinholes in the B-layer were excessive after the 500 °C anneal.

DETERMINATION AND EVOLUTION OF PHOTOELECTRICAL PARAMETERS BASED ON CUINSE2 AND CUINS2 HETEROSTRUCTURE UNDER ILLUMINATION.

In this paper, we study in the case of monochromatic and polychromatic illuminations, the behavior of the structure ZnO(n+)/CdS(n)/CuInSe2(p)/ CuInS2(p+) where CuInSe2 represent the base and CuInS2 the substrate. ZnO and CdS are used as window layers. We propose the study of the internal quantum efficiency, the generation rate profiles, the photogenerated minority carrier densities and the resulting photocurrent densities, represented versus the junction depth. We consider photon energy ranging between 1.04 eV (λ = 1.192 μm) and 3.1 eV (λ = 0.4 μm). The study of the profiles of these parameters allows to visualize the behavior of the photocreated carriers in the different regions of the structure, to identify the influence of the electrical and geometric parameters on the collection efficiency, shows the transport direction of the carriers and the effects of the interfaces and surfaces on their collection [1].

Measurement of Junction Depth in Sub-Micron Device Using SIMS Technique for Performance Estimation in RF Range

This chapter shows the measurement procedure of junction depth using SIMS method with detailed experimental procedure, and the result is verified by theoretical computation. SIMS profile is analytically characterized by Pearson's distribution function, and all the results together established the fact that the device can be utilized for operating as a diode in RF range; where ion dose is considered as a variable parameter with ion energy. Implanted impurity distribution profile is obtained as a function of depletion width from which junction depth can be evaluated. Straggle parameters and projected range profile near the ion energy range is computed for which depth is evaluated, and skewness & kurtosis are estimated to get a theoretical knowledge of all the moments assuming the Pearson IV distribution. Results suggest that distribution of atoms may be considered as Gaussian in nature.

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

Germanium Junctions for Beyond-Si Node Using Flash Lamp Annealing (FLA)

ABSTRACTWe report on the formation of shallow junctions with high activation in both n+/p and p+/n Ge junctions using ion implantation and Flash Lamp Annealing (FLA). The shallowest junction depths (Xj) formed for the n+/p and p+/n junctions were 7.6 nm and 6.1 nm with sheet resistances (Rs) of 860 ohms/sq. and 704 ohms/sq., respectively. By reducing knocked-on oxygen during ion implantation in the n+/p junctions, Rs was decreased by between 5% and 15%. The lowest Rs observed was 235 ohms/sq. with a junction depth of 21.5 nm. Hall measurements clearly revealed that knocked-on oxygen degraded phosphorus activation (carrier concentration). In the p+/n Ge junctions, we show that ion implantation damage induced high boron activation. Using this technique, Rs can be reduced from 475 ohms/sq. to 349 ohms/sq. These results indicate that the potential for forming ultra-shallow n+/p and p+/n junctions in the nanometer range in Ge devices using FLA is very high, leading to realistic monolithically-integrated Ge CMOS devices that can take us beyond Si technology.