Intrinsic device parameter extraction method for zinc oxide-based thin-film transistors

We present a device parameter extraction method that enables the reliable extraction of the intrinsic device parameters of zinc oxide (ZnO) thin-film transistors (TFTs). By assuming that mobility and contact resistance were modeled as gate bias-dependent power-laws, we derived a current–voltage relationship that decoupled from the contact resistance effect. In accordance with this derived relationship, we extracted the intrinsic mobility and contact resistance using the modified method, the values being consistent with the parameters extracted using the four-probe method.

NBTI-Aware Power Gating Design with Dynamically Varying Stress Probability Control on Sleep Transistor

With the aggressive scaling of the transistor, Negative Bias Temperature Instability (NBTI) has become the most dominant aging effect which causes the device parameter to degrade over its lifetime. This device parameter degradation of logic gates in nanometer technology is a major concern for the reliability of the digital circuit. It becomes even more critical when it comes to power gating structure, as small NBTI effect on PMOS sleep transistor used in header-based power gating structure would seriously affect the reliability, performance of the whole logic circuit. The conventional method of mitigating the NBTI effect is to oversize the sleep transistor, but it also gives rise to leakage overhead. In this work, a novel NBTI aware power gating architecture is presented to improve the lifetime of the circuit. Here, sleep transistors (STs) are switched ON/OFF periodically and a greater number of STs are turned ON, when NBTI related degradation reaches to its threshold value so that STs get more time to anneal NBTI degradation and improve its lifetime. Simulation result on ISCAS’85 benchmark circuits shows for 40% sleep signal, an average of 51.2% and 14% lifetime improvement with respect to the conventional over-sizing (OS) technique and normal stress probability control method, respectively with some power and area overhead.

The Impact of Interfacial Charge Trapping on the Reproducibility of Measurements of Silicon Carbide MOSFET Device Parameters

Silicon carbide is an emerging material in the field of wide band gap semiconductor devices. Due to its high critical breakdown field and high thermal conductance, silicon carbide MOSFET devices are predestined for high-power applications. The concentration of defects with short capture and emission time constants is higher than in silicon technologies by orders of magnitude which introduces threshold voltage dynamics in the volt regime even on very short time scales. Measurements are heavily affected by timing of readouts and the applied gate voltage before and during the measurement. As a consequence, device parameter determination is not as reproducible as in the case of silicon technologies. Consequent challenges for engineers and researchers to measure device parameters have to be evaluated. In this study, we show how the threshold voltage of planar and trench silicon carbide MOSFET devices of several manufacturers react on short gate pulses of different lengths and voltages and how they influence the outcome of application-relevant pulsed current-voltage characteristics. Measurements are performed via a feedback loop allowing in-situ tracking of the threshold voltage with a measurement delay time of only 1 μs. Device preconditioning, recently suggested to enable reproducible BTI measurements, is investigated in the context of device parameter determination by varying the voltage and the length of the preconditioning pulse.