Using statistical inverse methods for detecting defects in electronic components

The thermal modeling of electronic components is mandatory to optimize the cooling design versus reliability. Indeed most of failures are due to thermal phenomena [1]. Some of them are neglected or omitted by lack of data: ageing, manufacturing issues like voids in glue or solder joints, or material properties variability. Transient measurements of the junction-to-board temperature supply real thermal behavior of the component and PCB assembly to complete these missing data[2]. To complement and supplement the numerical model, inverse methods identification based on a statistical deconvolution approach, such as Bayesian one, is applied on these measurements to extract a Foster RC thermal network. The identification algorithm performances have been demonstrated on numerical as well as experimental dataset. Furthermore defects or voids can be detected using the extracted Foster RC networks.

Thermal Cycling Test and Simulation of Fan-Out Chip-Last Panel-Level Packaging for Heterogeneous Integration

In this study, the reliability of the solder joints of a heterogeneous integration of one large chip (10 × 10 mm) and two smaller chips (7 × 5 mm) by a fan-out method with a redistribution layer-first substrate fabricated on a 515 × 510-mm panel is investigated. Emphasis is placed on the thermal cycling test (−55°C Δ 125°C, 50-min cycle) of the heterogeneous integration package on a printed circuit board (PCB). The thermal cycling test results are plotted into a Weibull distribution. The Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope and the true 10% life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at the test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the PCB assembly of the heterogeneous integration package are provided and discussed. A nonlinear, time- and temperature-dependent 3-D finite element simulation is performed for the heterogeneous integration PCB assembly and correlated with the thermal cycling test results.

Indirect System Condition Monitoring Using Online Bayesian Changepoint Detection

This paper presents a method for online vibration analysis and a simple test bench analogue for the solder pumping system in an industrial wave-soldering machine at a Siemens factory. A common machine fault is caused by solder build-up within the pipes of the machine. This leads to a pressure drop in the system, which is replicated in the test bench by restricting the flow of water using a gate valve. The pump’s vibrational response is recorded using an accelerometer. The captured data is passed through an online Bayesian Changepoint Detection algorithm, adapted from existing literature, to detect the point at which the change in flow rate affects the pump, and thus the PCB assembly capability of the machine. This information can be used to trigger machine maintenance operations, or to isolate the vibrational response indicative of the machine fault.

Six-Side Molded Panel-Level Chip-Scale Package with Multiple Diced Wafers

In this study, the design, materials, process, assembly, and reliability of a six-side molded panel-level chip-scale package (PLCSP) are presented. Emphasis is placed on the fabrication of the redistribution layers (RDLs) of the PLCSP on a large temporary panel with multiple device wafers. Because all the printed circuited board (PCB) panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized. Thus, it is very high throughput. Because all the processes/equipment are PCB processes/equipment (not semiconductor process/equipment), it is a very low-cost process. After the fabrication of RDLs, the wafers from the PCB panel were debonded. It is followed by solder ball mounting and fabricating the six-side molded PLCSP from the original device wafers with RDLs. The drop test and the results including failure analysis of the PLCSP are presented. Thermal cycling of the six-side molded PLCSP PCB assembly is performed by a nonlinear temperature- and time-dependent finite-element simulation.

Six-Side Molded Panel-Level Chip Scale Package with Multiple Diced Wafers

In this study, the design, materials, process, assembly, and reliability of a 6-side molded panel-level chip scale package (PLCSP) are presented. Emphasis is placed on the fabrication of the RDLs (redistribution layers) of the PLCSP on a large temporary panel with multiple device wafers. Since all the printed circuited board (PCB) panels are in rectangular shape, some of the device wafers are diced into two or more pieces so the panel is fully utilized. Thus, it is very high throughput. Since all the processes/equipment are PCB process/equipment (not semiconductor process/equipment), it is a very low cost process. After the fabrication of RDLs, the wafers from the PCB panel are debonded. It is followed by solder ball mounting and fabricating the 6-side molded PLCSP from the original device wafers with RDLs. The drop test and the results including failure analysis of the PLCSP are presented. Thermal cycling of the 6-side molded PLCSP PCB assembly is performed by a nonlinear temperature- and time-dependent finite-element simulation.

Assessment of Fatigue Induced Pad Cratering With a Universal Expression of Printed Circuit Board Fatigue Resistance

Repeated loading is an important reason to cause pad cratering fatigue failure in ball grid array (BGA) device in printed circuit board (PCB) assembly. For industry application, the board level drop test is commonly applied to evaluate the pad cratering fatigue strength under the repetitive drop loading. Although this testing method is consistent with the actual service condition of BGA-PCB assembly, it is extremely time consuming in the testing operation and expensive in costs. Another fatigue evaluation testing method for BGA-PCB assembly is the board level cyclic bending test. Compare with the board level drop test, this testing method can be handled by universal testing machine automatically without manual operation during the testing process. In consequence, the cyclic bending test has the merits of simple, fast, and low costs, and it is always desirable to evaluate the repeated drop life of pad cratering with cyclic bending test. This research proposes a correlation between the cyclic bending and repetitive drop test in BGA-PCB assemblies. With assistance of finite element method, the equivalent cyclic bending testing conditions of drop tests are developed. The experimental validation is also conducted to prove accuracy of the correlation. From the analysis of finite element method and experiments, both cyclic bending tests and repetitive drop tests agree with the same strain–number of cycle (S–N) curve. This means the S–N curve can be treated as a generalized failure criterion of fatigue induced pad cratering. The conclusion is crucial for reliability design phases to prevent the pad cratering fatigue failure.