A new opportunity for the emerging tellurium semiconductor: making resistive switching devices

The development of the resistive switching cross-point array as the next-generation platform for high-density storage, in-memory computing and neuromorphic computing heavily relies on the improvement of the two component devices, volatile selector and nonvolatile memory, which have distinct operating current requirements. The perennial current-volatility dilemma that has been widely faced in various device implementations remains a major bottleneck. Here, we show that the device based on electrochemically active, low-thermal conductivity and low-melting temperature semiconducting tellurium filament can solve this dilemma, being able to function as either selector or memory in respective desired current ranges. Furthermore, we demonstrate one-selector-one-resistor behavior in a tandem of two identical Te-based devices, indicating the potential of Te-based device as a universal array building block. These nonconventional phenomena can be understood from a combination of unique electrical-thermal properties in Te. Preliminary device optimization efforts also indicate large and unique design space for Te-based resistive switching devices.

The Formal Design Models of a Universal Array (UA) and its Implementation

Arrays are one of the most fundamental and widely applied data structures, which are useful for modeling both logical designs and physical implementations of multi-dimensional data objects sharing the same type of homogeneous elements. However, there is a lack of a formal model of the universal array based on it any array instance can be derived. This paper studies the fundamental properties of Universal Array (UA) and presents a comprehensive design pattern. A denotational mathematics, Real-Time Process Algebra (RTPA), allows both architectural and behavioral models of UA to be rigorously designed and refined in a top-down approach. The conceptual model of UA is rigorously described by tuple- and matrix-based mathematical models. The architectural models of UA are created using RTPA architectural modeling methodologies known as the Unified Data Models (UDMs). The physical model of UA is implemented using linear list that is indexed by an offset pointer of elements. The behavioral models of UA are specified and refined by a set of Unified Process Models (UPMs). As a case study, the formal UA models are implemented in Java. This work has been applied in a number of real-time and nonreal-time systems such as compilers, a file management system, the real-time operating system (RTOS+), and the ADT library for an RTPA-based automatic code generation tool.

The Formal Design Models of a Universal Array (UA) and its Implementation

Arrays are one of the most fundamental and widely applied data structures, which are useful for modeling both logical designs and physical implementations of multi-dimensional data objects sharing the same type of homogeneous elements. However, there is a lack of a formal model of the universal array based on it any array instance can be derived. This paper studies the fundamental properties of Universal Array (UA) and presents a comprehensive design pattern. A denotational mathematics, Real-Time Process Algebra (RTPA), allows both architectural and behavioral models of UA to be rigorously designed and refined in a top-down approach. The conceptual model of UA is rigorously described by tuple- and matrix-based mathematical models. The architectural models of UA are created using RTPA architectural modeling methodologies known as the Unified Data Models (UDMs). The physical model of UA is implemented using linear list that is indexed by an offset pointer of elements. The behavioral models of UA are specified and refined by a set of Unified Process Models (UPMs). As a case study, the formal UA models are implemented in Java. This work has been applied in a number of real-time and nonreal-time systems such as compilers, a file management system, the real-time operating system (RTOS+), and the ADT library for an RTPA-based automatic code generation tool.