Design of In-Memory Parallel-Prefix Adders

Computational methods in memory array are being researched in many emerging memory technologies to conquer the ‘von Neumann bottleneck’. Resistive RAM (ReRAM) is a non-volatile memory, which supports Boolean logic operation, and adders can be implemented as a sequence of Boolean operations in the memory. While many in-memory adders have recently been proposed, their latency is exorbitant for increasing bit-width (O(n)). Decades of research in computer arithmetic have proven parallel-prefix technique to be the fastest addition technique in conventional CMOS-based binary adders. This work endeavors to move parallel-prefix addition to the memory array to significantly minimize the latency of in-memory addition. Majority logic was chosen as the fundamental logic primitive and parallel-prefix adders synthesized in majority logic were mapped to the memory array using the proposed algorithm. The proposed algorithm can be used to map any parallel-prefix adder to a memory array and mapping is performed in such a way that the latency of addition is minimized. The proposed algorithm enables addition in O(log(n)) latency in the memory array.

A Novel Set of Base-Prime Floating Point Numbers

Presenting a novel set generalizing the usual base representation of floating point numbers. This "base-prime" set was identified in patented research on nonuniform data sampling and self-stabilizing computer arithmetic.<br>

A Novel Set of Base-Prime Floating Point Numbers

Presenting a novel set generalizing the usual base representation of floating point numbers. This "base-prime" set was identified in patented research on nonuniform data sampling and self-stabilizing computer arithmetic.<br>

A Novel Algorithm to Evaluate Definite Integrals by the Gauss-Legendre Integration Rule Based on the Stochastic Arithmetic: Application in the Model of Osmosis System

Finding the optimal iteration of Gaussian quadrature rule is one of the important problems in the computational methods. In this study, we apply the CESTAC (Controle et Estimation Stochastique des Arrondis de Calculs) method and the CADNA (Control of Accuracy and Debugging for Numerical Applications) library to find the optimal iteration and optimal approximation of the Gauss-Legendre integration rule (G-LIR). A theorem is proved to show the validation of the presented method based on the concept of the common significant digits. Applying this method, an improper integral in the solution of the model of the osmosis system is evaluated and the optimal results are obtained. Moreover, the accuracy of method is demonstrated by evaluating other definite integrals. The results of examples illustrate the importance of using the stochastic arithmetic in discrete case in comparison with the common computer arithmetic.

High-Performance RNS Modular Exponentiation by Sum-Residue Reduction

Modular exponentiation is fundamental in computer arithmetic and is widely applied in cryptography such as ElGamal cryptography, Diffie-Hellman key exchange protocol, and RSA cryptography. Implementation of modular exponentiation in residue number system leads to high parallelism in computation, and has been applied in many hardware architectures. While most RNS based architectures utilizes RNS Montgomery algorithm with two residue number systems, the recent modular multiplication algorithm with sum-residues performs modular reduction in only one residue number system with about the same parallelism. In this work, it is shown that high-performance modular exponentiation and RSA cryptography can be implemented in RNS. Both the algorithm and architecture are improved to achieve high performance with extra area overheads, where a 1024-bit modular exponentiation can be completed in 0.567 ms in Xilinx XC6VLX195t-3 platform, costing 26,489 slices, 87,357 LUTs, 363 dedicated multipilers of $18\times 18$ bits, and 65 Block RAMs.