scholarly journals Design of In-Memory Parallel-Prefix Adders

2021 ◽  
Vol 11 (4) ◽  
pp. 45
Author(s):  
John Reuben
Keyword(s):  
Computer Arithmetic ◽  
Boolean Logic ◽  
Von Neumann ◽  
Majority Logic ◽  
Memory Array ◽  
Emerging Memory ◽  
Non Volatile Memory ◽  
Parallel Prefix ◽  
Prefix Adder ◽  
Prefix Adders

Computational methods in memory array are being researched in many emerging memory technologies to conquer the ‘von Neumann bottleneck’. Resistive RAM (ReRAM) is a non-volatile memory, which supports Boolean logic operation, and adders can be implemented as a sequence of Boolean operations in the memory. While many in-memory adders have recently been proposed, their latency is exorbitant for increasing bit-width (O(n)). Decades of research in computer arithmetic have proven parallel-prefix technique to be the fastest addition technique in conventional CMOS-based binary adders. This work endeavors to move parallel-prefix addition to the memory array to significantly minimize the latency of in-memory addition. Majority logic was chosen as the fundamental logic primitive and parallel-prefix adders synthesized in majority logic were mapped to the memory array using the proposed algorithm. The proposed algorithm can be used to map any parallel-prefix adder to a memory array and mapping is performed in such a way that the latency of addition is minimized. The proposed algorithm enables addition in O(log(n)) latency in the memory array.

scholarly journals Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

2020 ◽  
Vol 10 (3) ◽  
pp. 28
Author(s):  
John Reuben
Keyword(s):  
Integrated Circuits ◽  
Logic Gates ◽  
Expressive Power ◽  
Boolean Logic ◽  
Majority Gate ◽  
Von Neumann ◽  
Majority Logic ◽  
Memory Array ◽  
Memory Wall ◽  
Parallel Prefix

As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives.

scholarly journals Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders

2018 ◽  
Vol 7 (2) ◽  
pp. 115
Author(s):  
Nehru.K K ◽  
Nagarjuna T ◽  
Somanaidu U
Keyword(s):  
High Performance ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Transmission Technique ◽  
Look Ahead ◽  
Parallel Prefix ◽  
Prefix Adder ◽  
Signal Processors ◽  
Prefix Adders ◽  
Better Than

<span>Parallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes<strong> </strong>with the lowest transistor<strong> </strong>count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the computation speed.The spice tool is used for analysis with different supply voltages.</span>

scholarly journals Design a High Speed Multiplier using Two Phase PPA

2019 ◽  
Vol 8 (11S2) ◽  
pp. 146-149
Keyword(s):  
High Speed ◽  
Two Phase ◽  
Ripple Carry Adder ◽  
Product Generation ◽  
Different Types ◽  
Effective System ◽  
Parallel Prefix ◽  
Three Stages ◽  
Prefix Adder ◽  
Prefix Adders

Basically, multiplier is an efficient superconductor logic which performs various switching operation. Here different types of adders are analysed using different methodologies. In this paper we introduced a multiplier using proposed PPA. It uses parallel prefix adders in their reduction phase and it is an effective system for faster results and optimised. The entire operation of proposed system depends upon three stages they are multiplier partial product generation, reduction stages and parallel prefix adder which is discussed in below sections. The delay gets reduced by achieving low logical depth in the system. So the Proposed system reduces the delay. From the proposed system we can observe that there is a reduction in delay and complexity. Compared to ripple carry adder and carry save adder, proposed system gives better results.

scholarly journals Design and Implementation of Kogge Stone adder using CMOS and GDI Design: VLSI Based

2019 ◽  
Vol 8 (6S3) ◽  
pp. 2181-2182 ◽  
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Input Information ◽  
Design And Implementation ◽  
Parallel Prefix ◽  
Distinctive Structure ◽  
Prefix Adder ◽  
Prefix Adders

Adders is a significant part in different math legitimate activity. Parallel Prefix Adder was developed as the most basic and effective circuit for double expansion. The Particular structure and execution are alluring for VLSI usage. In these papers, I can depict the structure and execution of the Kogge Stone Parallel Prefix Adders and actualized utilizing diverse plan procedure. CMOS (Complementary Metal Oxide Semiconductor) and GDI (Gate Diffusion Input) are the distinctive structure system utilized. . The plan and reenactment of rationale entryways is performed on CADENCE Design Suit 6.1.6 utilizing virtuoso and ADE Environment at GPDK 180nm innovation. The execution estimation considered for the presentation of the KSA is delay, number of door check/Transistor Count (territory) and power. Recreation reads are accomplished for 4-piece, 8-piece and 16-piece input information

scholarly journals Design and Implementation of High Speed Area Efficient Carry Select Adder Using Spanning Tree Adder Technique

2018 ◽  
pp. 21-26
Author(s):  
Hima Bindu Vykuntam ◽  
Chennaiah M ◽  
Sudhakar K
Keyword(s):  
Spanning Tree ◽  
High Speed ◽  
Computation Time ◽  
Digital Design ◽  
Comparative Performance ◽  
Ripple Carry Adder ◽  
Parallel Prefix ◽  
Carry Select Adder ◽  
Prefix Adder ◽  
Prefix Adders

In this paper, we propose Carry Select Adder (CSLA) architecture with parallel prefix adder. Instead of using 4-bit Brent Kung Adder (BKA), another parallel prefix adder i.e., 4-bit spanning Tree (ST) adder is used to design CSA. Because Adders are key element in digital design, which are not only performing addition operation, but also many other function such as subtraction, multiplication and division. A Ripple Carry Adder (RCA) gives the most complicated design as-well-as longer computation time so that we may gone for parallel prefix adders. This time critical application we use Spanning tree parallel prefix adder to drive fast results but they lead to increase in area. Proposed Carry Select Adder understands between RCA and BKA in term of area and delay. Delay of Existing adders is larger therefore we have replaced those with Brent Spanning Tree parallel prefix adder which gives fast result. This paper describes comparative performance of 4-bit RCA and 4-Bit BK parallel prefix adders with Our Proposed Spanning Tree adder based carry select adder designed using Xilinx ISE tool.

scholarly journals Design of Parallel Prefix Adder and Subtractor using Majority Logic Formulations

2020 ◽  
Vol 981 ◽  
pp. 042077
Author(s):  
Divya Gampala ◽  
L Srinivas ◽  
Vaseem Ahmed Qureshi
Keyword(s):  
Majority Logic ◽  
Parallel Prefix ◽  
Prefix Adder

scholarly journals Binary Addition in Resistance Switching Memory Array by Sensing Majority

Micromachines ◽  
2020 ◽  
Vol 11 (5) ◽  
pp. 496 ◽  
Author(s):  
John Reuben
Keyword(s):  
Energy Efficient ◽  
Full Adder ◽  
Resistance Switching ◽  
Boolean Logic ◽  
Majority Gate ◽  
Efficient Manner ◽  
Computing Systems ◽  
Von Neumann ◽  
Memory Array ◽  
Memory Wall

The flow of data between processing and memory units in contemporary computing systems is their main performance and energy-efficiency bottleneck, often referred to as the ‘von Neumann bottleneck’ or ‘memory wall’. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic, and in many nanotechnologies, it has been found to be an efficient logic primitive. In this paper, a technique is proposed to implement a majority gate in a memory array. The majority gate is realised in an energy-efficient manner as a memory R E A D operation. The proposed logic family disintegrates arithmetic operations to majority and NOT operations which are implemented as memory R E A D and W R I T E operations. A 1-bit full adder can be implemented in 6 steps (memory cycles) in a 1T–1R array, which is faster than I M P L Y , N A N D , N O R and other similar logic primitives.

Low Power Parallel Prefix Adder

2014 ◽  
Vol 573 ◽  
pp. 194-200 ◽  
Author(s):  
P. Kowsalya ◽  
M. Malathi ◽  
Palaniappan Ramanathan
Keyword(s):  
Low Power ◽  
Power Saving ◽  
Fundamental Operation ◽  
Parallel Prefix ◽  
Power Delay Product ◽  
Prefix Adder ◽  
Prefix Adders

Addition is a fundamental operation of all Arithmetic and Logic Units (ALU).The speed of addition operation decides the computational frequency of ALU. In order to improve the performance of the binary adder, the parallel prefix adder are preferred. There are various parallel prefix adders available. This work focuses on designing 8-bit prefix adders such as Brent Kung ,Kogge Stone and Sklansky adders using GDI technique. The performance of these GDI based prefix adders are compared with that of CMOS based prefix adder. GDI based prefix adders out performs CMOS based prefix adders in terms of power delay product (PDP). The design is implemented and simulated by DSCH2 and MICROWIND tool .The simulation result reveal about 31%,40% and 50 % of power saving is attained and the number of transistors also reduced.

Realization of Enhanced LMS Filter Using Carry Skip Adder And Quantum Dot Cellular Automation In VLSI For Removing Impulse Noises In Medical Image

2019 ◽  
Vol 14 ◽  
Author(s):  
K.R. Shankarkumar ◽  
Gokul Kumar
Keyword(s):  
Adaptive Filtering ◽  
Adaptive Filters ◽  
Pass Band ◽  
Least Mean Square ◽  
Low Pass ◽  
Parallel Prefix ◽  
Loop Feedback ◽  
Band Pass ◽  
The Difference ◽  
Prefix Adder

: Filtering is an important step in the field of image processing to suppress the required parts or to remove any artifacts present in it. There are different types of filters like low pass, high pass, Band pass, IIR, FIR and adaptive filtering etc.., in these filters adaptive filters is an important filter because it is used to remove the noisy signal and images. Least Mean Square filter is a type of an adaptive filtering which is used to remove the noises present in the medical images. The working of LMS is based on the minimization of the difference between the error images using a closed loop feedback. Therefore presented technique called as Q-CSKA. Here the CSKA performs its operation in stages which is based on the nucleus stage. In the traditional CSKA the nucleus stage is depend on the parallel prefix adder in this work it is replaced by the QCA adder. The QCA adder utilizes the less area compared to PPA and it can be realized in Nanometer range also. For multiplexers, And OR Invert, OR and Invert logic is used to reduce the area and delay. Due to these advantages of the QCA, AOI-OAI logic the proposed method outperformed the LMS implementation in area, power, and accuracy and delay, this based five type image noise of medical pictures related to the best technique is out comes. It helps to medicinal practitioner to resolve the symptoms of patient with ease.

Sign in / Sign up

Export Citation Format

Share Document