An Inter-Subband Processing Algorithm for Complex Clutter Suppression in Passive Bistatic Radar

Clutter suppression is a challenging problem for passive bistatic radar systems, given the complexity of actual clutter scenarios (stationary, time-varying and fractional-order clutter). Such complex clutter induces intense sidelobes in the entire range-Doppler plane and thus degrades target-detection performance, especially for low-observable targets. In this paper, a novel method, denominated as the batch version of the extensive cancellation algorithm (ECA) in the frequency domain (ECA-FB), is presented for the first time, to suppress stationary clutter and its sidelobes. Specifically, in this method, the received signal is first divided into short batches in the frequency domain to coarsen the range resolution, and then the clutter is removed over each batch via ECA. Further, to suppress the time-varying clutter, a Doppler-shifted version of ECA-FB (ECA-FBD) is proposed. Compared with the popular ECA and ECA-B methods, the proposed ECA-FB and ECA-FBD obtained superior complex clutter suppression and slow-moving target detection performance with lower computational complexity. A series of simulation and experimental results are provided to demonstrate the validity of the proposed methods.

On a Real-Time Blind Signal Separation Noise Reduction System

Blind signal separation has been studied extensively in order to tackle the cocktail party problem. It explores spatial diversity of the received mixtures of sources by different sensors. By using the kurtosis measure, it is possible to select the source of interest out of a number of separated BSS outputs. Further noise cancellation can be achieved by adding an adaptive noise canceller (ANC) as postprocessing. However, the computation is rather intensive and an online implementation of the overall system is not straightforward. This paper intends to fill the gap by developing an FPGA hardware architecture to implement the system. Subband processing is explored and detailed functional operations are profiled carefully. The final proposed FPGA system is able to handle signals with sample rate over 20000 samples per second.